Trigger of high speed and low power consumption

Abstract

The invention discloses a trigger of high speed and low power consumption. The trigger comprises a control signal generation circuit, an enablement unit and a latch register structure, n the latch register structure comprises two input ends, two output ends, two enablement ends and a grounding end; the enablement unit comprises two enablement circuits; an output signal X and an external control signal D of the control signal generation circuit serve as input signals of the first enablement circuit, and the output end of the first enablement circuit is connected with the first enablement end; and anti-phase signals DB of the output signal X and the external control signal D of the control signal generation circuit serves as input signals of the second enablement circuit, and the output end of the second enablement circuit is connected with the second enablement end. Compared with a traditional structure, the circuit structure of the trigger in the invention is simpler; and the parasitic capacitance of the output end of a latch register is very low, the speed of the trigger is improved, and there is no static power consumption.

Description

technical field [0001] The invention belongs to the technical field of analog or digital-analog hybrid integrated circuits, and relates to a high-speed and low-power consumption trigger. Background technique [0002] As an important sequential circuit structure, flip-flop is widely used in digital, analog and analog-digital hybrid integrated circuits. In recent years, with the continuous development of integrated circuit manufacturing technology, the demand for high-speed low-power flip-flops has gradually increased. In order to meet the requirements of low power consumption, the power supply voltage has been further reduced. In response to this trend, in order to ensure the working performance of flip-flops , developed some high-speed low-power flip-flop structures, including SAFF (sense amplifier based flip-flop) structure, MSAFF (modified sense amplifier based flip-flop) and SBFF (self-blocking flip-flop) structure, the above three structures have their own advantages and...

AI Technical Summary

Problems solved by technology

However, the control signal generation circuit and the enable transistor of the latch are both composed of NMOS transistors connected in series, and the on-resistance is relatively large. At the same time, the parasitic capacitance at the output end of the flip-flop is also relatively large, which is not suitable for high-speed circuit design.

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