Read data signal processing circuit for DDR (Double Data Rate) memory, and read data processing method

Abstract

The invention discloses a read data signal processing circuit for a DDR (Double Data Rate) memory, and a read data processing method. The read data signal processing circuit comprises a sampling and receiving module and a pulse width the testing module, wherein the sampling and receiving module is connected with the pulse width the sting module when a coding numerical value corresponding to a digital control signal TD [n-1:0] corresponds to the period of a data pulse selection signal DQS; and according to the digital control signal TD [n-1:0], 1 / 4 of the period of the data pulse selection signal DQS is additionally delayed for the data pulse selection signal DQS, so that a maximum time sampling window can be obtained when the data pulse selection signal DQS samples a data signal DQ. The technical scheme is controlled and processed by digital coding, and instant work can be realized.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a read data signal processing circuit and a read data processing method of a DDR memory. Background technique [0002] In SOC (System-on-a-Chip) applications, for a double-rate synchronous dynamic random access memory (Double Data Rate SDRAM, DDR SDRAM) connected to the chip, according to the timing requirements of the DDR SDRAM read operation, during the read operation , The data edge pulse and the data pulse edge are aligned, and the DDR SDRAM controller needs to sample data and latch the data in a short time, so as to realize sampling 2 data in two clock cycles. The prior art basically adopts a phase-locked loop (PLL) architecture or a delay-locked loop (DLL) architecture for clock delay design. [0003] In order to meet the timing requirements of the main control SOC receiving external DDR signals, a clock function module is designed inside the general main control chip ...

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Problems solved by technology

[0007] However, based on the phase-locked loop PLL architecture or the delay-locked loop DLL architecture, there will be two problems. One is power consumption. Maintaining the phase-locked loop PLL or delay-locked loop DLL requires additional power consumption. The other is Speed ​​problem, phase-locked loop PLL circuit or delay phase-locked loop DLL circuit takes a long time to be stable, if for power consumption considerations, when the main control chip does not exchange data with the external DDR memory, it often needs to perform low In power consumption mode, the phase-locked loop PLL and delay-locked loop DLL need to be turned off. When the main control chip needs to resume access to the external DDR memory, the phase-locked loop PLL and delay-locked loop DLL functional modules resume normal operation The state also takes some time

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