Integrated circuit layout design method, layout design system and manufacturing method

Abstract

The invention discloses a layout design method, a layout design system and a manufacturing method of an integrated circuit, including: designing the initial topological structure of the integrated circuit and the initial size of each transistor of the integrated circuit, and obtaining the size of each transistor of the integrated circuit The preset value range of the parameters related to the layout effect; the pre-simulation of the initial topology of the integrated circuit, the initial size of each transistor and the preset value range of the parameters related to the layout effect of each transistor, in order to meet the preset yield rate The target layout design parameters of the integrated circuit, the target layout design parameters include the target topology of the integrated circuit and the target size of each transistor of the integrated circuit, and the target value of the relevant parameters of the layout effect of each transistor of the integrated circuit; according to the target layout design Parameters, design the target layout of the integrated circuit that meets the preset performance, ensure the yield rate of the integrated circuit, and improve the long design cycle of the existing design layout.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, and more specifically, relates to a layout design method, a layout design system and a manufacturing method of an integrated circuit. Background technique [0002] Today, with the continuous advancement of integrated circuit technology to the node process, the feature size of transistors has also increased from the previous micron level to the nanometer level. Due to the further shrinking of the size of the transistor, the characteristics of the transistor itself are more significantly affected by the layout dependent effect, such as the influence of the well proximity effect and the shallow trench isolation stress effect, which in turn leads to the production yield of the integrated circuit. Low. Contents of the invention [0003] In view of this, the present invention provides a layout design method, a layout design system and a manufacturing method of an integrated circu...

AI Technical Summary

Problems solved by technology

Due to the further shrinking of the size of the transistor, the characteristics of the transistor itself are more significantly affected by the layout dependent effect, such as the influence of the well proximity effect and the shallow trench isolation stress effect, which in turn leads to the production yield of the integrated circuit. Low

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