SM4 algorithm realization system of pipeline structure

Abstract

The invention relates to an SM4 algorithm realization system of a pipeline structure. An input buffer module, an internal four-level water turbine function module, an output buffer module, a storage module, a constant generating operation module and a control module are included. An enable signal is received, a mode control signal is obtained and parsed, key expansion operation, encryption operation and decryption operation are completed according to the mode control signal, and encryption result data and decryption result data are obtained and output. The realization system employs a non-linear S box for displacement operation, the non-linear S box uses random mask and addition mask technology of PPRM structure and a single-wheel iteration internal four-level pipeline structure, and compared with the prior art, the realization area is small, the safety level is high, resistance to zero-value attack is high, the operation speed is higher, the power consumption of operation is lower, and the application prospect is better.

Description

technical field [0001] The invention relates to the field of realizing the SM4 algorithm, in particular to a system for realizing the SM4 algorithm with a pipeline structure. Background technique [0002] In 2012, the State Cryptography Administration of China announced the SM4 algorithm standard. The SM4 algorithm has good speed, power consumption and security advantages, and is of great significance to both the wireless LAN industry and commercial cryptography research. However, with the popularization of handheld devices and smart cards and the rapid dissemination of information, higher requirements are placed on the computing speed and power consumption of the SM4 algorithm hardware circuit. In addition, the differential power analysis technology has a high success rate of simple attacks on cryptographic circuits. Therefore, higher requirements are put forward for the security of the SM4 algorithm hardware circuit. [0003] The implementation of the round function opera...

AI Technical Summary

Problems solved by technology

When a single-round iterative structure is adopted, the algorithm circuit only needs a small hardware resource consumption, but the corresponding data processing speed is relatively slow, which cannot meet the current high-speed data transmission.

When the round-level pipeline structure is adopted, its circuit can have a higher data processing speed, but the corresponding hardware resource consumption is relatively large

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