A method of forming a germanium channel layer of an nmos transistor device, an nmos transistor device, and a cmos device

Abstract

A method of forming a germanium channel layer for an NMOS transistor device, the method comprising: a. providing a trench having sidewalls defined by a dielectric material structure and adjoining a surface of a silicon substrate; b. a seed layer is grown in said trench on said surface, said seed layer has a front surface comprising facets with a (111) orientation; c. said crystal in said trench planting a strain relaxation buffer layer on the seed layer, the strain relaxation buffer layer comprising silicon germanium; d. planting a channel layer comprising germanium (Ge) on the strain relaxation buffer layer; and related NMOS transistor devices and CMOS devices .

Description

technical field [0001] The present invention relates to methods of fabricating germanium channel layers of transistor devices, preferably NMOS transistor devices, and related devices. Background technique [0002] In CMOS production, it is often desirable to have a combination of tensile strained / unstrained and compressively strained channel structures for each NOMS and PMOS transistor device on a single substrate. [0003] Prior art solutions are to provide different channel materials for the channel structure (channel layer) for tensile and compressive strain. [0004] The use of channel materials such as Ge-based or III-V-based poses particular problems. At advanced technology nodes, there is an urgent need for channel materials with higher mobility compared to conventional strained and unstrained Si channel reference devices, aiming to further enhance device performance. [0005] Therefore, commercial use of germanium-based channel materials is considered to be state o...

AI Technical Summary

Problems solved by technology

Poor mobility using standard gate stacks has been widely reported in conventional planar Ge nFETs (e.g. with (100)-Ge as the main carrier transport plane)

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