Three-dimensional semiconductor memory device and method of fabricating the same

Abstract

A semiconductor memory device is provided including a substrate; a stack structure including gate electrodes vertically stacked on the substrate; a vertical channel part penetrating the gate electrodes; a dopant region provided in the substrate at a side of the stack structure; a common source plug on the substrate and electrically connected to the dopant region; and cell contact plugs connected to the gate electrodes, respectively. A top surface of the common source plug is at a different level from top surfaces of the cell contact plugs.

Description

technical field [0001] The inventive concepts relate generally to semiconductor devices, and more particularly, to semiconductor memory devices and methods of manufacturing the same. Background technique [0002] Semiconductor devices have been highly integrated to provide high performance and reduce cost. Specifically, the integration density of a semiconductor memory device will directly affect the cost of the semiconductor memory device. The integration density of a conventional two-dimensional (2D) memory device may be mainly determined by the area occupied by a unit memory cell, and thus may be greatly affected by a technique for forming a fine pattern. However, since extremely expensive devices are required to form fine patterns, the integration density of 2D memory devices continues to increase but is still limited. [0003] To overcome these limitations, 3D semiconductor memory devices including three-dimensionally arranged memory cells have been developed. Conte...

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Problems solved by technology

However, the integration density of 2D memory devices continues to increase but remains limited due to the need for extremely expensive devices to form fine patterns

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