A kind of manufacturing method of vdmos device and vdmos device

Abstract

The invention provides a manufacturing method of a VDMOS device and the VDMOS device. The VDMOS device comprises a first conductive type substrate, a first conductive type epitaxial layer located on a first surface of the first conductive type substrate, a second conductive type body area of first concentration located in the first conductive type epitaxial layer, a first conductive type source area located in the second conductive type body area of the first concentration, a first oxide layer located on the first conductive type epitaxial layer, a silicon nitride layer located on the first oxide layer, a second conductive type body area of second concentration located in a contact hole, a polycrystalline silicon layer located on the silicon nitride layer, a second oxide layer located on the silicon nitride layer and the polycrystalline silicon layer, a first metal layer located in the second conductive type body area of the second concentration and on the second oxide layer and a second metal layer located on a second surface of the first conductive type substrate, wherein the silicon nitride layer forms the contact hole through etching. Because a manufacturing flow of the VDMOS device relates to photoetching of the contact hole, a cellular integration degree is low. By using the method and the device of the invention, the above problem is solved.

Description

technical field [0001] The invention relates to the technical field of semiconductor chip manufacturing technology, in particular to a method for manufacturing a VDMOS device and the VDMOS device. Background technique [0002] The manufacturing process of conventional planar VDMOS devices in the prior art involves photolithography of contact holes. However, the photolithography of contact holes involves registration deviation, and the actual manufactured contact holes may be left or right. This results in that the distance between adjacent polysilicon strips cannot be too small, otherwise it will cause a short circuit between the polysilicon and the contact hole. This means that the degree of cell integration (reflected in the width of polysilicon strips and the spacing between adjacent polysilicon strips) is affected. Contents of the invention [0003] The technical problem to be solved by the present invention is to provide a method for manufacturing a VDMOS device and ...

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Problems solved by technology

[0003] The technical problem to be solved by the present invention is to provide a method for manufacturing a VDMOS device and a VDMOS device, so as to solve the problem of low cell integration in the prior art due to the photolithography of contact holes involved in the manufacturing process of VDMOS devices

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