Control circuit for improving frequency limit of sensitive amplifier
A technology of sensitive amplifiers and control circuits, applied in the direction of instruments, static memory, digital memory information, etc., can solve the problems of small system clock cycle range and limit system performance, so as to expand cycle range, improve system performance, and improve frequency limit Effect
Active Publication Date: 2016-10-26
XI AN UNIIC SEMICON CO LTD
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Problems solved by technology
[0013] In order to solve the technical problem that the system clock cycle range corresponding to the existing sense amplifier control circuit is too small and limits the system performance, the present invention provides a control circuit that improves the frequency limit of the sense amplifier
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[0025] Embodiments of the present invention will be further described below in conjunction with the accompanying drawings.
[0026] Such as Figure 4 as shown, Figure 4It is a design schematic diagram of a control circuit for improving the frequency limitation of the sense amplifier in the present invention. Including inverters U0-U3, delay unit U5, two-input AND gate U4, two-input NAND gates U6, U7. The sense amplifier delay SADLY is connected to the input of the inverter U0. The first sense amplifier delay inversion SAE_N1 is connected to the output of the inverter U0, connected to the input of the inverter U1, and also connected to an input of the two-input NAND gate U7. The sense amplifier enable SAE is connected to the output of inverter U1 and the input of inverter U2. The delay inversion SAE_N2 of the second sense amplifier is connected to the output of the inverter U2, and also connected to an input of the two-input NAND gate U6. The read enable RE is connected t...
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The invention relates to a control circuit for improving frequency limit of a sensitive amplifier. The control circuit comprises a phase inverter U0, a phase inverter U1, a phase inverter U2, a phase inverter U3, a two-input AND gate U4 and a time delay unit U5, an output end of the phase inverter U0 is connected with the phase inverter U1 and a two-input NAND gate U7 respectively, an output end of the phase inverter U1 outputs sensitive amplifier enable (SAE) and is connected with an input end of the phase inverter U2, and the phase inverter U2 is connected with one input end of a two-input NAND gate U6; an output end of the time delay unit U5 is connected with an input end of the two-input AND gate U4, an output end of the two-input AND gate U4 is connected with the two-input AND gate U6 and the phase inverter U3 respectively, and the phase inverter U3 is connected with the two-input NAND gate U7. The technical problem that a system clock period range corresponding to an existing sensitive amplifier control circuit is too narrow is solved; in the control circuit, the minimum period of a system clock is improved, and period range of the system clock is expanded.
Description
technical field [0001] The invention relates to the field of memory design, in particular to a control circuit for improving the frequency limitation of a sense amplifier. Background technique [0002] Sense amplifiers are widely used in memory read operations to amplify small signals on bit lines into digital signals. The upper frequency limit of the sense amplifier and its control circuit usually determines the upper frequency limit of the memory system using the sense amplifier and its control circuit. [0003] see figure 1 , figure 1 Create a schematic for a typical sense amplifier circuit. Including, pull-down amplifying NMOS transistors N0, N1, pull-up amplifying PMOS transistors P2, P3, current switch NMOS transistor N2, amplifying line SL / SL_N pre-charging and equalizing PMOS transistors P4-P6, output driving inverter I0, I1, input Switch PMOS transistors P0, P1. [0004] The input voltage is positive IN_P connected to the source of P0. The input voltage is rev...
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IPC IPC(8): G11C7/06
CPCG11C7/062
Inventor 熊保玉
Owner XI AN UNIIC SEMICON CO LTD