Apparatus and method for controlling rounding when performing floating point operation

Abstract

An apparatus and a method are provided for controlling rounding when performing a floating point operation. The apparatus has argument reduction circuitry to perform an argument reduction operation, and is provided with reduce and round circuitry that generates from a supplied floating point value a modified floating point value to be input to the argument reduction circuitry. The reduce and round circuitry is arranged to modify a significand of the supplied floating point value, based on a specified value N, in order to produce a truncated significand with a specified rounding applied, the truncated significand being N bits shorter than the significand of the supplied floating point value, and then being used as a significand for the modified floating point value. The specified value N is chosen such that the argument reduction operation performed using the modified floating point value will inhibit roundoff error in a result of the argument reduction operation. By enabling roundoff error to be inhibited in the way, it is possible to use such argument reduction circuitry in the computation of a number of floating point operations while enabling the correct rounded result to be obtained.

Description

technical field [0001] The disclosed technology relates to an apparatus and method for controlling rounding when performing floating point operations. Background technique [0002] There are various floating point operations that are generally expensive to perform accurately, in terms of the complexity of the circuitry required to produce the result and / or the computational time required. One such floating point operation is a floating point division operation in which a first floating point number is divided by a second floating point number. To perform a precise floating point division operation, many clock cycles are typically taken for execution, which can significantly affect the performance of the processing circuitry implementing the division operation. Although one can try to build dedicated logic circuitry to increase the performance of this division operation, doing so would significantly increase the cost and complexity of the resulting processing circuitry (eg, ...

AI Technical Summary

Problems solved by technology

To perform an exact floating-point division operation, many clock cycles are typically taken to execute, which can significantly affect the performance of the processing circuitry implementing the division operation

Although skilled artisans can seek to construct dedicated logic circuitry to increase the performance of this division operation, doing so would significantly increase the cost and complexity of the resulting processing circuitry (eg, in terms of silicon area cost and high verification effort)

[0003] In general, techniques that manage to perform floating-point division with less impact on performance are not guaranteed to produce completely accurate results for floating-point division operations

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