Apparatus and method for controlling rounding when performing floating point operations

Abstract

Apparatus and methods are provided for controlling rounding when performing floating point operations. The device has argument reduction circuitry to perform an argument reduction operation, and additionally provides reduction and rounding circuitry that produces a modified floating point value from a supplied floating point value for input to Argument reduction circuitry. The reduction and rounding circuitry is arranged to modify the significand of the provided floating point value based on the specified value N so as to produce a truncated significand that is greater than the significand of the provided floating point value with the specified rounding applied. N bits shorter, and then used as the significand of the modified floating-point value. The specified value N is chosen such that an argument reduction operation performed using the modified floating point value will suppress round-off errors in the result of the argument reduction operation. By enabling rounding errors to be suppressed in this way, it is possible to use this argument reduction circuitry in the calculation of numerous floating point operations while enabling accurate rounding results to be obtained.

Description

technical field [0001] The disclosed technology relates to an apparatus and method for controlling rounding when performing floating point operations. Background technique [0002] There are various floating point operations that are generally expensive to perform accurately, in terms of the complexity of the circuitry required to produce the result and / or the computational time required. One such floating point operation is a floating point division operation in which a first floating point number is divided by a second floating point number. To perform a precise floating point division operation, many clock cycles are typically taken for execution, which can significantly affect the performance of the processing circuitry implementing the division operation. Although one can try to build dedicated logic circuitry to increase the performance of this division operation, doing so would significantly increase the cost and complexity of the resulting processing circuitry (eg, ...

AI Technical Summary

Problems solved by technology

To perform an exact floating-point division operation, many clock cycles are typically taken to execute, which can significantly affect the performance of the processing circuitry implementing the division operation

Although skilled artisans can seek to construct dedicated logic circuitry to increase the performance of this division operation, doing so would significantly increase the cost and complexity of the resulting processing circuitry (eg, in terms of silicon area cost and high verification effort)

[0003] In general, techniques that manage to perform floating-point division with less impact on performance are not guaranteed to produce completely accurate results for floating-point division operations

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