Mass Erasing Device for Phase Change Memory

Abstract

The invention provides an integral erasure device of a phase-change memory. On the basis of an excising phase-change memory, the integral erasure device comprising an erasure enable switch, a word line voltage generation circuit, an erasure voltage generation circuit, a bit line erasure switching circuit and word line erasure switches is mainly added independently to avoid limitations of a binary-system one-hot coding decoder. The integral erasure device of the phase-change memory has the advantages that when the integral erasure device is capable of erasing enable signals integrally effectively, all word line erasure switches are switched on, all gate tubes of all phase-change storage units are turned on, and erasure voltage is transmitted to bit lines through the bit line erasure switching circuit to erase the phase-change memory quickly, so that the defect that the whole phase-change memory is erased for a long time every time and tens of thousands of, millions of and even more times of erasure operation is required due to the fact that the phase-change memory has no one-time integral erasure function in the prior art is overcome effectively.

Description

technical field [0001] The invention relates to the erasing technical field of an information memory, in particular to an overall erasing device of a phase-change memory. Background technique [0002] Phase change random access memory (Phase change random access memory; PCRAM) is a non-volatile random access memory, and the phase change memory unit is the basic unit of phase change memory, which is the basis of storage, such as figure 1 Shown is a 1T1R (1transistor and 1resistance) phase-change memory array 4 composed of n*m phase-change memory cells 41. The phase-change memory array occupies most of the area of ​​the phase-change memory chip, and consists of a large number of crossed bit lines ( BL) 42 and word lines (WL) 43 form a two-dimensional planar matrix, and form a phase-change memory cell 41 at each cross point. The word line and the bit line are respectively selected by the external address signal through the column selector of the row decoder and the column deco...

AI Technical Summary

Problems solved by technology

[0003] In summary, phase change memory can only be used for a single phase change memory unit (1bit output phase change memory) or n phase change memory units (n bits parallel output) when n bits are operated in parallel. phase-change memory) to perform an erase operation, specifically, for a phase-change memory with a 1-bit output, at most only one bit line of the phase-change memory array is selected at the same time, and only one word line is selected , then, only one phase-change memory unit can be selected in the phase-change memory array at the same time, taking the PCRAM chip with 1M storage capacity and 1bit output as an example, it has 1024 word lines and 1024 bit lines, according to binary one-hot translation The principle of the code circuit, only one word line WL and one bit line BL can be selected in one operation, and the operation time for erasing a single memory cell is about 500ns. If the entire memory array needs to be erased, it needs to execute 1024*1024= 1048576 erasing operations, the time to erase the entire storage array is as high as about 0.5s! And performing millions of operations greatly increases the complexity of the operation; for a phase-change memory with n bits parallel output, although n pieces of memory array bit lines can be selected at the same time, generally there are only 8 / 16 bits. Due to the limitation of pin area, operation complexity, and market application, the number of n bits parallel output generally does not exceed 32, and only one word line can be selected. Then, at the same time, the phase change memory array with n bits parallel output Only n phase-change memory cells can be selected for erasing operation, and n<32

Take the PCRAM chip with 1M storage capacity and 16bits output as an example. It has 1024 word lines and 1024 bit lines. According to the principle of binary one-hot decoding circuit, only one word line and 16 bit lines can be selected in one operation. That is to say, only 16 phase-change memory cells can perform erasing operations at the same time, and the operation time of erasing a single phase-change memory cell is about 500ns. If the entire memory array needs to be erased, it is necessary to execute 1024 *1024 / 16=65536 erasing operations, the time to erase the entire storage array is as high as 32ms! And tens of thousands of operations need to be performed to increase the complexity of the operation

[0004] Therefore, it is necessary to propose an overall erasing device for phase-change memory that overcomes various deficiencies in the prior art, so as to avoid problems such as being limited by the binary one-hot code decoder and greatly affecting the erasing efficiency.

Images