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Systems and methods for adaptive read level adjustment

A level, storage system technology, applied in the direction of responding to the generation of errors, non-redundancy-based fault handling, read-only memory, etc., can solve problems such as not being effective

Active Publication Date: 2020-04-28
WESTERN DIGITAL TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, many read level scaling algorithms are not efficient at determining when and how to adjust

Method used

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  • Systems and methods for adaptive read level adjustment
  • Systems and methods for adaptive read level adjustment
  • Systems and methods for adaptive read level adjustment

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Embodiment Construction

[0013] The detailed description set forth below is intended as a description of various configurations of the present disclosure and is not intended to represent the only configurations in which the present disclosure may be practiced. The accompanying drawings are incorporated herein and constitute a part of the Detailed Description. The detailed description includes specific details for the purpose of providing a thorough understanding of the present disclosure. It will be apparent, however, that the present disclosure may be practiced without these specific details. In some instances, structures and components are shown in block diagram form in order to avoid obscuring the concepts of the disclosure. For ease of understanding, the same parts are marked with the same element numbers.

[0014] The flash memory is read using the read level voltage. When the read level voltage is set to an optimum level, a bit error rate (BER) can be minimized. However, as the lifetime of t...

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Abstract

The requested data is read from the flash memory using a first read level voltage. A number of first bit value errors and a number of second bit value errors are determined from the read requested data. An error ratio of the number of errors in the first bit value to the number of errors in the second bit value is compared to an error rate range. The first read level voltage is adjusted based on the comparison of the error ratio to the error ratio range.

Description

Background technique [0001] The present disclosure relates to solid state memory, such as flash memory, and in particular to adjusting read levels for reading data stored in solid state memory. As the lifespan of the flash memory or the number of times of data retention increases, the programming level distribution of the flash memory cells tends to scatter and shift, resulting in an increased read error rate. Adjusting the read level as the flash life or data retention times increases can reduce the read error rate. However, many read level adjustment algorithms are not efficient at determining when and how to adjust. Contents of the invention [0002] The subject technology relates to a method for managing a data storage system, the method comprising: reading requested data from flash memory using a first read level voltage; the number of first bit-value errors and the number of second bit-value errors; and the number of first bit-value errors and the number of second bi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/10G11C16/26G11C16/34
CPCG06F11/1068G11C16/26G11C16/3404G06F11/1048G11C29/50004G11C29/52G11C2029/0411G11C11/5642G11C29/02G06F11/0727G06F11/076G06F11/079G06F11/0793
Inventor A.G.科梅蒂
Owner WESTERN DIGITAL TECH INC