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Logic implementation device of input clock stabilizing circuit

A technology for inputting clocks and stabilizing circuits, applied to electrical components, generating electric pulses, pulse generation, etc., can solve the problem of uncertain initial value of D flip-flop power-on, mutual deadlock of clock/reset functions, and difficulty in handling testability design And other issues

Active Publication Date: 2018-01-09
SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT +1
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AI Technical Summary

Problems solved by technology

[0009] ①. A clock delay stabilization circuit module is implemented by a conventional D flip-flop with a reset circuit, but during the asynchronous reset operation of the chip, the clock/reset functions in the conventional D flip-flop with a reset circuit may be mutually de

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  • Logic implementation device of input clock stabilizing circuit
  • Logic implementation device of input clock stabilizing circuit
  • Logic implementation device of input clock stabilizing circuit

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Embodiment Construction

[0032] Attached below Figure 2-Figure 4 , the specific embodiment of the present invention will be further described in detail.

[0033] see figure 2 , figure 2 Shown is the block diagram of the logic implementation device of the input clock stabilization circuit of the present invention. Such as figure 2 As shown, the clock delay stabilization circuit module is used in digital logic circuits, which may include a test mode input terminal test_mode, a clock signal input terminal clk_in, and a clock signal output terminal clk_out. The clock delay stabilization circuit module adopted in the present invention can make the input clock of the clock signal input terminal clk_in stable after a period of time after power-on, and then the internal D flip-flop is driven by the clock signal clk_in.

[0034] The logic implementation device of the input clock stabilization circuit is divided into four functional modules (M cascaded frequency division units, delay stabilization unit,...

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Abstract

The invention provides a logic implementation device of an input clock stabilizing circuit, applied to a digital logic circuit. The logic implementation device comprises a clock delay stabilizing circuit module, the clock delay stabilizing circuit module comprises a clock signal input end clk-in, a clock signal output end clk-out, a plurality of cascaded frequency dividing units, a delay stabilizing unit and a clock gating unit Clock-Gating-Cell. By adoption of the logic implementation device, after the clock signal input in a digital logic chip is stable after a period of time, the D triggerin the digital logic chip obtains the clock signal. In addition, the logic implementation device supports DFT test, the output clk-out of the digital logic circuit module is equal to the input clk-indue to the test mode control signal test-mode so as to ensure the complete controllability of the digital logic circuit module.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, in particular to the logic design of chip hardware, in particular to a logic implementation device for an input clock stabilization circuit. Background technique [0002] see figure 1 , figure 1 Shown is an equivalent circuit diagram of a digital logic circuit chip in the prior art. As shown in the figure, digital logic circuit chips are divided into two categories according to their structural characteristics: combinational logic circuit modules (referred to as combinational circuit modules) and sequential logic circuit modules (referred to as sequential circuit modules). The sequential logic circuit module in the digital logic circuit chip is a logic circuit with a memory function, and the memory element generally adopts a D type flip-flop (D type flip-flop, DFF for short). [0003] D flip-flops are widely used and can be used as digital signal registers, shift registers,...

Claims

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Application Information

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IPC IPC(8): H03K3/356
Inventor 李林张小亮张远袁庆史汉臣李琛温建新
Owner SHANGHAI INTEGRATED CIRCUIT RES & DEV CENT
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