A Logic Realization Device of Input Clock Stabilization Circuit

Abstract

The invention provides a logic implementation device of an input clock stabilizing circuit, applied to a digital logic circuit. The logic implementation device comprises a clock delay stabilizing circuit module, the clock delay stabilizing circuit module comprises a clock signal input end clk-in, a clock signal output end clk-out, a plurality of cascaded frequency dividing units, a delay stabilizing unit and a clock gating unit Clock-Gating-Cell. By adoption of the logic implementation device, after the clock signal input in a digital logic chip is stable after a period of time, the D triggerin the digital logic chip obtains the clock signal. In addition, the logic implementation device supports DFT test, the output clk-out of the digital logic circuit module is equal to the input clk-indue to the test mode control signal test-mode so as to ensure the complete controllability of the digital logic circuit module.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to the logic design of chip hardware, in particular to a logic implementation device for an input clock stabilization circuit. Background technique [0002] see figure 1 , figure 1 Shown is an equivalent circuit diagram of a digital logic circuit chip in the prior art. As shown in the figure, digital logic circuit chips are divided into two categories according to their structural characteristics: combinational logic circuit modules (referred to as combinational circuit modules) and sequential logic circuit modules (referred to as sequential circuit modules). The sequential logic circuit module in the digital logic circuit chip is a logic circuit with a memory function, and the memory element generally adopts a D type flip-flop (DFF for short). [0003] D flip-flops are widely used and can be used as digital signal registers, shift registers, frequency division, and w...

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Problems solved by technology

[0009] ①. A clock delay stabilization circuit module is implemented by a conventional D flip-flop with a reset circuit, but during the asynchronous reset operation of the chip, the clock / reset functions in the conventional D flip-flop with a reset circuit may be mutually dead the condition of the lock;

[0010] ② Another clock delay stabilization circuit module is designed using a D flip-flop without a reset function, so the initial value of the D flip-flop is uncertain when it is powered on, and it is difficult to handle Design for Testability (DFT for short) logic

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