Co-frequency co-time full duplex receiver time domain infrastructure and signal receiving method in wireless communication
A simultaneous wireless communication technology with the same frequency, applied in the field of communication, can solve the problems of poor anti-interference ability, achieve the effect of eliminating anti-interference at the same frequency, enhancing anti-interference ability, and improving anti-interference ability
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Embodiment 1
[0043] The block diagram of the time-domain architecture of the same-frequency and simultaneous full-duplex receiver for wireless data communication in this embodiment includes:
[0044] Adaptive high-frequency signal amplifier, multiple auxiliary carrier detection circuits, multiple signal control switches, multiple sampling circuits, multiple ADC converters, multiple time recorders, multiple sampling frequency regulators, a signal operation circuit, a Circuits such as DAC converters make up the receiver.
[0045] Such as figure 2 As shown, the specific steps are as follows:
[0046] S101a, amplifying the high-frequency signal, amplifying the signal received by the antenna to a suitable amplitude value;
[0047] S102a, auxiliary carrier 1 signal detection, auxiliary carrier 1 signal cyclic detection, when the indication signal of the receiver is detected, enter the detection channel process;
[0048] S103a, open the switch 1 and the timer 1, let the signal enter the sampl...
Embodiment 2
[0056] Such as image 3 As shown, the specific steps are as follows:
[0057] S101b, amplifying the high-frequency signal, amplifying the signal received by the antenna to a suitable amplitude value;
[0058]S102b. Auxiliary carrier 2 signal detection, auxiliary carrier 2 signal cyclic detection, when the indication signal is detected, enter the detection channel process, record and lock, and other indication signals are detected by the next channel;
[0059] S103b, open the switch 2 and the timer 2, allow the signal to enter the sampler 2, and record the time;
[0060] S104b, the sampler 2 performs signal sampling in a specified manner;
[0061] S105b, the 2-channel ADC of the sampler converts the sampling signal into a digital signal, and transmits it to the arithmetic unit;
[0062] S106b. The arithmetic unit performs channel signal calculation according to a specified algorithm;
[0063] S107b. Save the channel operation data;
[0064] S108b, save the channel recordin...
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