A structure and related method for expanding the number of resistance states of a memristor

Abstract

The invention relates to a structure for expanding the number of resistance states of a memristor and a related method, which can realize the structure for expanding the number of resistance states ina memristor cross array and comprise cross array units, resistance state expansion function line groups, input line groups, output line groups and unit connection line groups, Wherein the resistancestate expansion function line group passes through a plurality of resistance state expansion function lines of which the tail ends are first gating devices; Each two adjacent transverse lines or longitudinal lines in the cross array unit are connected, each first gating device enables a signal path of a resistance state expansion function line to be connected or disconnected according to signals of a control end, memristors connected to the transverse lines or the longitudinal lines receiving input signals are connected in parallel, and resistance state expansion is achieved. The invention also discloses a method for realizing the expansion of the number of resistance states in the memristor cross array and a method for writing the resistance values of the memristors in the cross array. The method has the advantages that power failure is not prone to losing, and the requirement for the multi-resistance state in mass weighted summation of the neural network is met.

Description

technical field [0001] The invention relates to the field of neural network deep learning, in particular to a structure for realizing expansion of the number of resistance states in a memristor cross array, an expansion method and a writing method. Background technique [0002] Artificial intelligence research is becoming more and more popular, and the deep learning of neural networks has become the research focus of many scientific research projects. In order to adapt to the application requirements of data weighted summation in a large number of neural network deep learning, the crossbar type multiplication and addition unit has attracted much attention. However, if you still use the traditional CMOS design ideas to design logic circuits, it is difficult to use the advantages of the crossbar structure to achieve a large number of weight multiplication and addition. One of the main reasons is that the storage of information in CMOS circuits is volatile, and the depth of eac...

AI Technical Summary

Problems solved by technology

The decline in weight accuracy directly leads to a sharp increase in the number of neural network layers and the number of neurons in a single-layer network, which takes up too much hardware resources

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