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Method for performing page availability management of memory device, memory device and electronic device

A memory device and usability technology, applied in the field of flash memory access, can solve problems such as write and read test failures, data errors, etc., to achieve the effect of optimizing performance

Active Publication Date: 2019-11-22
SILICON MOTION INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When trying to apply the downgraded flash die to the manufacture of smaller capacity memory devices, various problems may occur in these memory devices installed with the downgraded flash die, such as data errors, writing during production, etc. read test failure etc.

Method used

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  • Method for performing page availability management of memory device, memory device and electronic device
  • Method for performing page availability management of memory device, memory device and electronic device
  • Method for performing page availability management of memory device, memory device and electronic device

Examples

Experimental program
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Embodiment Construction

[0041] I. Memory system

[0042] figure 1It is a schematic diagram of an electronic device 10 according to an embodiment of the present invention, wherein the electronic device 10 includes a host device (host device) 50 and a memory device 100 . The main device 50 may include: at least one processor 52 (such as one or more processors), used to control the operation of the main device 50; and a power supply circuit 54, coupled to the at least one processor 52, used to provide power To the above-mentioned at least one processor 52 and memory device 100, and output one or more driving voltages to the memory device 100, wherein the memory device 100 can be used to provide storage space to the host device 50, and can obtain the one or more driving voltages from the host device 50 A driving voltage is used as the power supply of the memory device 100. Examples of the host device 50 may include (but are not limited to): multifunctional mobile phones, tablet computers, wearable devi...

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PUM

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Abstract

The invention discloses a method for performing page availability management of a memory device, an associated memory device and electronic device, and a page availability management system. A methodfor performing page availability management of a memory device, the associated memory device and electronic device, and page availability management system are provided. The method may include: obtaining a set of page Error Correction Code (ECC) error tables of a non-volatile (NV) memory; based on a predetermined rule, finding respective local risky pages of at least one portion of blocks within aplurality of blocks according to the set of page ECC error tables, respectively, to generate local risky page counts respectively corresponding to page indexes; finding one or more global risky pagescorresponding to one or more page indexes of the multiple page indexes according to the local risky page counts; and writing a global risky page table into the memory device, for controlling the memory device to skip using the one or more global risky pages of each of the plurality of blocks.

Description

technical field [0001] The present invention relates to the access of flash memory (Flash memory), especially a method for page availability management (page availability management) of memory devices, related memory devices and electronic devices, and page availability management systems . Background technique [0002] In recent years, due to the continuous development of memory technology, various portable or non-portable memory devices (for example: memory cards conforming to SD / MMC, CF, MS, XD or UFS standards; : An embedded storage device conforming to the UFS or EMMC specification) is widely implemented in many applications. Therefore, access control of memory in these memory devices has become a very hot topic. [0003] As far as the commonly used NAND flash memory is concerned, it can be mainly divided into two types of flash memory: single level cell (SLC) and multiple level cell (MLC). Each transistor in the single-level cell flash memory, which is regarded as a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10G11C29/42
CPCG06F11/1068G11C29/42G11C2029/0411G11C2029/0409G11C29/52G06F3/0679G06F3/0619G06F3/0629G06F12/0246G06F2212/1032G06F2212/7207G06F2212/7204G06F3/0644G06F3/0604G11C29/883G06F3/0616
Inventor 吴柏纬
Owner SILICON MOTION INC
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