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Simultaneously multi-threaded processor

A technology of synchronous multi-threading and processors, applied in the direction of electrical digital data processing, instruments, machine execution devices, etc., to achieve the effect of real-time data storage operations

Active Publication Date: 2021-12-03
SPREADTRUM COMM (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In the prior art, when the processor is performing pipeline operations, if there is a data storage operation concurrently at this time, the data storage operation usually needs to be performed after the operation instructions on the pipeline are completed, and real-time data storage cannot be realized when the pipeline is busy.

Method used

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Embodiment Construction

[0022] refer to figure 1 , a schematic diagram of the structure of an existing processor is given. figure 1 Among them, a pipeline (Pipeline) 101 is connected to an index RAM (Tag RAM) 102, a storage buffer (Store Buffer) 103, a data high-speed RAM (Data RAM) 104, and an instruction management unit (Request Management) 105, respectively. The index RAM 102, the storage buffer 103, and the data high-speed RAM 104 are all storage units.

[0023] The data loading instruction can be output to the pipeline 101 through the instruction management unit 105 . when figure 1 When the processor in the processor performs data loading processing, all loading instructions will pass through the pipeline 101 . When there is a data loading instruction on the pipeline 101 , first check whether there is an address corresponding to the data loading instruction in the index RAM 102 , that is, determine whether the data loading instruction hits in the index RAM 102 . When the address correspondin...

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Abstract

A synchronous multi-thread processor, comprising: an index RAM, a storage buffer, a data cache, and at least two pipelines, wherein: the at least two pipelines are respectively connected to the index RAM, the storage cache, and the The data caches are all connected, and are suitable for accessing the data caches; each pipeline corresponds to an independent thread, and at least one pipeline is an interruptible pipeline, and at least one pipeline is a non-interruptible pipeline, wherein: the interruptible pipeline The interrupt pipeline is adapted to stop a currently executing non-data storage instruction and execute the data storage instruction when a data storage instruction is received. The above solution can realize real-time data storage operation.

Description

technical field [0001] The invention relates to the field of processors, in particular to a synchronous multi-thread processor. Background technique [0002] A cache is an integral part of the memory subsystem. A cache temporarily stores data in memory to provide fast access for the processor. The cache structure of the cache can be multi-layered, such as a first-level cache and a second-level cache. In the prior art, caches can be further divided into data caches and instruction caches according to different stored data. [0003] Synchronous Multi-Threading (Simultaneous Multi-Threading, SMT) is a technology that optimizes resource utilization efficiency on a chip. In an SMT processor, storage resources can be multiplexed by different hardware threads, and computing resources such as floating-point units, arithmetic logic units, and caches are shared by multiple threads. [0004] In the prior art, when the processor is performing pipeline operations, if there is a data ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
CPCG06F9/3867
Inventor 纪忠良刘培军叶正国安武牧叶超华少雄刘新潮曹效伦杨柳西
Owner SPREADTRUM COMM (SHANGHAI) CO LTD
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