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Simultaneously multi-threaded processor

A technology of synchronous multi-threading and processors, applied in the fields of electrical digital data processing, instruments, machine execution devices, etc., can solve the problem of high cost and achieve the effect of real-time data storage operations

Active Publication Date: 2021-11-23
SPREADTRUM COMM (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the number of bits of the processor increases, the cost of increasing the number of processing bits corresponding to the corresponding pipeline becomes higher and higher.

Method used

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  • Simultaneously multi-threaded processor

Examples

Experimental program
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Embodiment Construction

[0026] refer to figure 1 , a schematic diagram of the structure of an existing processor is given. figure 1 Among them, a pipeline (Pipeline) 101 is connected to an index RAM (Tag RAM) 102, a storage buffer (Store Buffer) 103, a data high-speed RAM (Data RAM) 104, and an instruction management unit (Request Management) 105, respectively. The index RAM 102, the storage buffer 103, and the data high-speed RAM 104 are all storage units.

[0027] The data loading instruction can be output to the pipeline 101 through the instruction management unit 105 . when figure 1 When the processor in the processor performs data loading processing, all loading instructions will pass through the pipeline 101 . When there is a data loading instruction on the pipeline 101 , first check whether there is an address corresponding to the data loading instruction in the index RAM 102 , that is, determine whether the data loading instruction hits in the index RAM 102 . When the address correspondin...

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PUM

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Abstract

A synchronous multi-threaded processor, comprising: an index RAM, a storage buffer, a data cache, and at least two pipelines, wherein: the at least two pipelines are respectively connected to the index RAM, the storage cache, and the The data caches are all connected, and are suitable for accessing the data caches; each pipeline has a one-to-one corresponding data cache area, and the data cache area is used for: when the corresponding pipeline receives the data to be stored When the number of bits is greater than the maximum number of data bits of the corresponding pipeline, store a part of the data corresponding to the data storage instruction; the data shifter is suitable for shifting the data in the data buffer area corresponding to different pipelines to restore The data to be stored is stored in the storage buffer. The above solution can use a pipeline with a lower number of bits to support a processor with a higher number of bits while realizing real-time data storage.

Description

technical field [0001] The invention relates to the field of processors, in particular to a synchronous multi-thread processor. Background technique [0002] A cache is an integral part of the memory subsystem. A cache temporarily stores data in memory to provide fast access for the processor. The cache structure of the cache can be multi-layered, such as a first-level cache and a second-level cache. In the prior art, caches can be further divided into data caches and instruction caches according to different stored data. [0003] Synchronous Multi-Threading (Simultaneous Multi-Threading, SMT) is a technology that optimizes resource utilization efficiency on a chip. In an SMT processor, storage resources can be multiplexed by different hardware threads, and computing resources such as floating-point units, arithmetic logic units, and caches are shared by multiple threads. [0004] In the prior art, when the processor is performing pipeline operations, if there is a data ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38
CPCG06F9/3814G06F9/3861G06F9/3869
Inventor 刘培军安武牧纪忠良叶正国叶超华少雄曹效伦刘新潮杨柳西
Owner SPREADTRUM COMM (SHANGHAI) CO LTD
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