Software and hardware interaction method and device for hardware accelerator and storage medium

Abstract

The invention provides a software and hardware interaction method and device for a time sequence accelerator and a storage medium, and the method comprises the steps: a main thread step: building a plurality of sub-threads, generating a compiler call instruction, and generating a corresponding queue; executing tasks of a plurality of assembly lines decomposed by a software and hardware interactionprocess based on a time sequence accelerator according to the plurality of sub-threads, the plurality of assembly lines comprising: a first assembly line for sending data to specified hardware; the second assembly line is used for sending an instruction and result related information to the specified hardware; the third assembly line sends a hardware calculation instruction; and a fourth pipelinefor reading the result data from the specified hardware, wherein the sub-threads execute the tasks of the four assembly lines in a parallel mode. The method provided by the embodiment of the invention can improve the utilization rate of hardware resources.

Description

technical field [0001] The present invention relates to the field of computer systems, and more specifically, to a method, device and storage medium for efficient interaction between software and hardware for time series accelerators. Background technique [0002] In the era of big data, with the development of technologies such as the Internet of Things, cloud computing, and the Internet, a large amount of data generated in various application scenarios is continuing to grow and accumulate on an astonishing scale. With the improvement of transistor technology, the quantum tunneling effect will become an unavoidable limitation, "Moore's Law" is about to expire, and human society is entering the "post-Moore era". Dedicated computing architecture has become an important opportunity in the "post-Moore era". Special-purpose chips ushered in the "golden" age of coprocessors. Dedicated chips basically adopt a design architecture similar to Single Instruction Multiple Data (SIMD:...

AI Technical Summary

Problems solved by technology

This process is a serial process, which leads to limited data transmission efficiency and long system waiting time, which affects the throughput of task processing and thus affects the utilization of hardware resources.

Images