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Dual-port SRAM

A dual-port, port structure technology, applied in static memory, instruments, etc., can solve the problem of slow reading speed, and achieve the effect of improving reading symmetry

Active Publication Date: 2020-06-26
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0027] It can be seen that the path of the current Iread1 to Iread4 is not a symmetrical structure, which will make the current Iread2 and Iread4 smaller than the current Iread1 and Iread3, and the corresponding reading speed will also be slower

Method used

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Examples

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Embodiment Construction

[0078] Please also refer to the circuit diagram of the SRAM cell structure of the dual-port SRAM of the embodiment of the present invention figure 1 as shown in Figure 5 As shown, it is the superimposed structural layout of the lower layer and the first metal layer 4 of the SRAM cell structure of the dual-port SRAM of the embodiment of the present invention; the SRAM cell structure of the dual-port SRAM of the embodiment of the present invention includes: the main body structure of the data storage unit, the first A port structure and a second port structure.

[0079] The main body structure of the data storage unit is formed by a first inverter and a second inverter cross-coupled to form a first storage node node1 and a second storage node node2 which are opposite to each other.

[0080] The first port structure includes a first selector PG1 and a second selector PG2, and the second port structure includes a third selector PG3 and a fourth selector PG4.

[0081] Both the p...

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Abstract

The invention discloses a dual-port SRAM (Static Random Access Memory). Four selection tubes corresponding to two ports of an SRAM unit structure are symmetrically arranged in a layout, and two selection tubes belonging to different ports and corresponding to the same storage node are arranged in the same active region, so that reading paths corresponding to different storage nodes are symmetricaland the same and do not comprise polycrystalline silicon circuits. According to the invention, the reading paths of each port to the two storage nodes are of a symmetrical structure, so that the reading currents of each port to the two storage nodes are symmetrical and consistent, the reading speeds of each port to the two storage nodes are symmetrical and consistent, and the reading symmetry ofthe dual-port SRAM is improved.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a dual-port static random access memory (SRAM). Background technique [0002] SRAM includes an array structure composed of multiple SRAM cell structures. In dual-port SRAM, each SRAM cell structure has two port structures. Each SRAM cell structure can be read and written through two port structures. The setting enables parallel operations on two different rows. Such as figure 1 is the circuit diagram of the SRAM cell structure of the existing dual-port SRAM, figure 1 The SRAM cell structure in is an 8T structure composed of 8 transistors. The SRAM cell structure of the dual-port SRAM includes: a data storage unit body structure, a first port (Port) structure and a second port structure, figure 1 , the first port is also the A port, and the second port is also the B port. [0003] The main body structure of the data storage unit is formed by a first inverter and a second ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C5/02G11C5/06
CPCG11C5/025G11C5/063
Inventor 陈品翰吴栋诚贾经尧
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD