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Test Algorithm and Device for 3D NAND Flash Memory

A test device and memory technology, applied in static memory, instruments, etc., can solve problems such as failure of memory device units, inability to cover 3D NAND Flash memory interference faults, etc.

Active Publication Date: 2022-07-05
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In the 3D NAND Flash memory, the storage device units form an array in three-dimensional direction, and there is an interference fault between the storage device units. generated by the set conditions, if there is a disturbance fault, it will cause the failure of the memory device unit
The current test algorithm is mainly used in the test of planar NAND Flash memory, which cannot cover the interference fault of 3D NAND Flash memory

Method used

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  • Test Algorithm and Device for 3D NAND Flash Memory
  • Test Algorithm and Device for 3D NAND Flash Memory
  • Test Algorithm and Device for 3D NAND Flash Memory

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Embodiment Construction

[0035] In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Many specific details are set forth in the following description to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, and those skilled in the art can do so without departing from the connotation of the present invention. Similar promotion, therefore, the present invention is not limited by the specific embodiments disclosed below.

[0037] As described in the Background Art, in 3D NAND Flash memory, memory device cells form an array in a three-dimensional direction, and there are interference failures between memory device cells, the interference failure is a failure of the insulating layer of the memory device cell m...

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Abstract

The present invention provides a test algorithm and device for 3D NAND Flash memory and 3D NAND Flash memory. Based on the structure of the 3D NAND Flash memory, and considering the failure model of the 3D NAND Flash memory, a new test method is proposed. Vectors can be tested for more coverage or further comprehensive coverage of 3D NAND Flash memory disturbance faults.

Description

technical field [0001] The invention relates to the field of memory testing, in particular to a testing algorithm and a device for a 3D NAND Flash memory. Background technique [0002] NAND Flash (flash memory) storage devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. With the advent of the era of big data, NAND devices with a planar structure are approaching the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, a 3D NAND Flash memory is proposed. [0003] In the 3D NAND Flash memory, the memory device cells form an array in three-dimensional direction, and there is an interference failure between the memory device cells, the interference failure is the failure of the insulating layer manufacturing of the memory device cell or due to electron bias in different operation modes of the memory. If there is an inter...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/12
CPCG11C29/12
Inventor 王颀张桔萍刘飞霍宗亮
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI