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Test algorithm and device for 3D NAND Flash memory

A test device and memory technology, applied in static memory, instruments, etc., can solve problems such as interference faults that cannot cover 3D NAND Flash memory, failure of memory device units, etc.

Active Publication Date: 2020-09-11
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

[0003] In the 3D NAND Flash memory, the storage device units form an array in three-dimensional direction, and there is an interference fault between the storage device units. generated by the set conditions, if there is a disturbance fault, it will cause the failure of the memory device unit
The current test algorithm is mainly used in the test of planar NAND Flash memory, which cannot cover the interference fault of 3D NAND Flash memory

Method used

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  • Test algorithm and device for 3D NAND Flash memory
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  • Test algorithm and device for 3D NAND Flash memory

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Embodiment Construction

[0035] In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

[0036] In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

[0037] As described in the background technology, in the 3D NAND Flash memory, the storage device units form an array in the three-dimensional direction, and there is an interference fault between the storage device units. The interference fault is a fault in the insulating layer of the storage device unit or in...

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Abstract

The invention provides a test algorithm and a test device for a 3D NAND Flash memory. Based on the structure of a 3D NAND Flash memory, in view of the fault model of the 3D NAND Flash memory, a new test method is provided, and tests are performed according to a specific test sequence and test vectors, so that interference faults of the 3D NAND Flash memory can be covered more or further comprehensively.

Description

technical field [0001] The invention relates to the field of memory testing, in particular to a testing algorithm and a device for a 3D NAND Flash memory. Background technique [0002] NAND Flash (flash memory) storage devices are non-volatile storage products with low power consumption, light weight and good performance, and are widely used in electronic products. With the advent of the era of big data, the planar NAND device is close to the limit of practical expansion. In order to further increase the storage capacity and reduce the storage cost per bit, 3D NAND Flash memory is proposed. [0003] In the 3D NAND Flash memory, the storage device units form an array in three-dimensional direction, and there is an interference fault between the storage device units. If there is a disturbance fault, it will cause the failure of the memory device unit. The current test algorithm is mainly used in the test of planar NAND Flash memory, and cannot cover the interference fault of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/12
CPCG11C29/12
Inventor 王颀张桔萍刘飞霍宗亮
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI