1588 synchronization method, system and device for high-speed tte cascade network

Abstract

The invention belongs to the technical field of network communication, and discloses a high-speed TTE cascaded network-oriented 1588 synchronization method, system, and device. The port calculates the link delay, the switching node receives the data frame, obtains the receiving time stamp, analyzes and extracts the synchronization frame Sync Frame content, cache timestamp information, calculate time offset, correct local clock, forward synchronization frame Sync to send port, send arbitration, send analysis and cache frame type, MAC send processing, get send timestamp, extract cached send frame type , to modify the Sync frame correction field to complete transparent transmission. The present invention adopts the method of analyzing the data frame type at the data link layer, and then performing MAC transmission processing, so that the time stamp can be quickly corrected when the synchronization frame is about to be transmitted to the high-speed network port; at the same time, the design switching node adopts a transparent clock plus a common The clock working mode improves the versatility and functional diversity of the synchronization scheme.

Description

technical field [0001] The invention belongs to the technical field of network communication, and in particular relates to a high-speed TTE cascaded network 1588 synchronization method, system and device. Background technique [0002] At present, the time-triggered Ethernet network is a time-deterministic network compatible with standard Ethernet. By adding a time-triggered method on the basis of traditional Ethernet, it provides a conflict-free and deterministic network for key control data services. transfer method. As the time-triggered Ethernet network data traffic increases, the network rate continues to increase, and the number of network terminals gradually increases, the typical star topology in the TTE network system can no longer meet the needs of data interaction. High-speed TTE network has become the focus of research. The real-time and deterministic nature of the time-triggered Ethernet network is based on a high-precision global synchronous clock. Therefore, ...

AI Technical Summary

Problems solved by technology

This method has the following deficiencies: the method of obtaining time stamps at the physical layer requires the use of a dedicated PHY chip that supports the IEEE 1588 protocol, and this method is inseparable from the central processing unit CPU to complete the analysis and calculation functions, resulting in a poor general-purpose synchronization solution. sex and transplantation

The disadvantage of this method is that it is only designed for the time synchronization scheme, and does not consider that other data frames and synchronization frames seize the MAC transmission channel, resulting in the synchronization frame being discarded by the MAC, and the stability of clock synchronization is affected; at the same time, the synchronization frame Frame analysis is performed when sending to the network port. When facing a high-speed network port, there will be a problem that the synchronization frame is sent by the network port before being parsed. The synchronization method is only applicable to low-speed network ports and has poor adaptability

[0006] Through the above analysis, the problems and defects of the existing technology are: the existing IEEE 1588 clock synchronization scheme is not suitable for TTE cascaded networks; it needs a dedicated PHY chip and CPU, which has poor versatility and portability; it is not suitable for high-speed The network does not consider the problem of synchronous frames and other data frames preempting the MAC transmission channel, which has poor stability and adaptability

[0007] The difficulty of solving the above problems and defects is: the two clock models proposed by the IEEE 1588 protocol suitable for switching nodes, the boundary clock and the transparent clock, both have their own defects, and it is necessary to expand a clock model to solve the defects of the boundary clock and the transparent clock , so it is suitable for TTE cascaded networks; in order to improve the symmetry of the synchronization link, the position of the synchronization frame to get the time stamp should be as close as possible to the bottom layer, but there is a problem that a dedicated PHY chip is required to get the time stamp at the physical layer; for For high-speed network ports, it is necessary to ensure that the frame type has been analyzed when the synchronous frame is sent, which is used to correct the timestamp field in time; there are other asynchronous data frames in the network, and it is necessary to consider the problem that the synchronous frame and other data frames occupy the MAC transmission channel

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