41 results about "Clock model" patented technology

The invention relates to the technical field of time synchronization, and provides a parameter-adaptive multi-sensor network time synchronization method and related equipment, and the method comprises the steps: building a clock model based on the deviation and offset of the local time of each sensor relative to the current moment; constructing an updating formula for updating the drift and offset of the local time of each sensor; constructing a time synchronization parameter adaptive model based on the update formula and all the clock models, and solving the time synchronization parameter adaptive model by using an optimization algorithm to obtain an optimal parameter set; updating the drift and the offset of each sensor by using the optimal parameter set and an updating formula to obtain the final drift and the final offset of each sensor at the current moment; and for each sensor, adjusting the local time of the sensor according to the final drift and the final offset of the sensor, so that the local time of all the sensors is synchronized. According to the method, the accuracy of time synchronization can be improved.

The invention belongs to the technical field of health assessment, and particularly relates to an aging clock construction method based on a causal machine joint model. The method comprises the steps of 1, obtaining a multi-modal data set of a target crowd based on multi-modal data fusion and standardization preprocessing; 2, performing two-stage screening on the multi-modal data set to obtain core features; 3, analyzing interaction among multiple groups of schools based on the extended proportion advantage logistic regression hybrid model, and then carrying out P value calibration based on a fused saddle point approximation method; 4, constructing an aging clock based on a mixed causal effect graph model, evaluating a multi-dimensional causal relationship, and calculating the biological age of the individual; according to the method, clinical phenotype data and multi-omics data are fused, a machine learning and causal inference combined method is adopted, the individual aging degree and health risk are accurately analyzed, a high-performance aging clock model is provided for primary medical institutions, and scientific basis and decision support are provided for health management and early disease intervention.

The invention discloses a time calibration method and system for a time synchronization network, and relates to the technical field of communication, and the method comprises the steps: installing a clock on each node in the network; time calibration of a master clock is realized by receiving signals of at least two navigation satellites and calculating a time difference between the satellites; message exchange is carried out between the master clock and the slave clock through a network; calculating network delay and clock offset between the master clock and the slave clock; constructing a transparent clock model, recording delay time passing through each node in a message, and performing compensation when network delay is calculated; dynamically selecting a path with lower network delay to perform message exchange between the master clock and the slave clock; and optimizing the clock skew between the master clock and the slave clock. The error calculation module and the error optimization module are arranged to eliminate the uncertainty of most of network delay and message exchange, so that the time synchronization precision is improved, and the long-term stability of synchronization is improved.

The invention provides a time synchronization method based on an IEEE 1588 protocol, and relates to the technical field of time synchronization. Comprising the following steps: firstly, establishing a network-based master-slave clock model to characterize a clock frequency; secondly, acquiring a timestamp set of master and slave clocks of the current round, and calculating average transmission delay and time offset; thirdly, a clock synchronization equation of Kalman filtering is built based on a clock model, time offset and drift serve as input, an optimal time offset value is obtained, and a local clock is adjusted to complete synchronization of the current round. Then, a new timestamp set is obtained for the next round, the average transmission delay and the time offset are calculated, and the optimal offset value is determined through a Kalman filtering equation; meanwhile, the number of cycles is calculated according to the offset value and the receiving timestamp, and frequency compensation is carried out on the slave clock. According to the invention, the problem of low time synchronization precision in the prior art is effectively solved.

The invention relates to a precise time synchronization parameter tracking method based on alternating minimization Kalman filtering, and belongs to the technical field of time synchronization. According to the method, timestamp noise is introduced into a clock synchronization parameter observation equation, and a state-space equation of clock synchronization parameter tracking is established in combination with a double-state clock model; a Kalman filtering method is used for tracking clock phase offset and frequency offset, and in the updating stage of Kalman filtering, an alternative minimization method is introduced for estimating the variance of timestamp noise and unknown observation noise in real time and correcting and updating Kalman gain. And furthermore, the influence of timestamp deviation and observation noise with unknown statistical characteristics on the clock synchronization parameter tracking precision is suppressed, and long-term effective tracking of the clock synchronization parameter is realized. According to the method, the problem that Kalman filtering is easy to diverge under unknown timestamp noise and observation noise is solved, joint tracking of clock phase offset and frequency offset can be realized, and the robustness and stability of clock synchronization are further improved.

The invention relates to the technical field of radio orientation, in particular to an enhanced Beidou precise time service method based on a receiver clock model, which comprises the following steps: acquiring multi-source data, and preprocessing the multi-source data; establishing a Beidou receiver clock model, optimizing model parameters through a least square method, outputting a first clock drift value and a first coefficient, and predicting a second clock drift value and a second coefficient by using a machine learning model; then, a Bayesian fusion model is utilized to be combined with the Beidou receiver clock model and the machine learning model, a clock drift predicted value is output, and a time migration predicted value is calculated; calculating a carrier-to-noise ratio loss value, an autocorrelation function distortion value and a phase change value, generating a signal quality index, and calculating an error compensation value by using a weight distribution mechanism; and finally, correcting the clock skew according to the error compensation value. Through combination of multiple models, the precision of clock drift prediction is improved, and the clock skew is effectively corrected, so that the precision of mountainous area time service is improved.

The invention discloses a self-adaptive frequency distributed clock synchronization method and system, a storage medium and equipment, and belongs to the field of clock synchroniss.The method comprises the steps that a clock model and a random time delay model are constructed, and in the random time delay model, random time delay is modeled into normal distribution; on the basis of the constructed clock model and the time delay model, clock parameters of the nodes are updated through a maximum likelihood estimation method, and each node estimates a logic clock of the node through two pieces of synchronous data information of neighbor nodes of the node; and adjusting the clock synchronization frequency according to the updated clock parameters of the nodes and the load of the distributed system. According to the method, the influence of random time delay on synchronization precision in communication time delay is reduced, a completely distributed synchronization method is adopted, a reference clock is not needed, the requirement for network topology is low, and fault tolerance is high; and meanwhile, the clock synchronization frequency can be adaptively adjusted, and software and hardware overhead is reduced.

The invention provides a digital-analog hybrid verification method for a clock chip, and the method comprises the steps: building a test top layer based on an analog circuit top layer of the clock chip, and extracting an analog verilog circuit model; completing module-level simulation by using an analog circuit to obtain a nonlinear parameter and a jitter clock parameter; the nonlinear parameters and the jitter clock parameters are inserted into a verilog circuit model to complete nonlinear modeling, and a digital-analog hybrid simulation environment is built in cooperation with a digital RTL / digital netlist; and applying test excitation in a digital-analog hybrid simulation environment to lock the phase-locked loop, and periodically acquiring data to calculate a jitter index so as to complete digital-analog hybrid simulation verification of the clock chip. According to the method, the nonlinear TDC, DTC and DCO models and the jitter clock model are introduced into the digital-analog hybrid verification of the clock chip, so that the simulation can be closer to a real scene, the simulation result is more reliable, and the simulation speed is higher.

The invention relates to a satellite-borne clock control method, device and system based on model prediction. The method comprises the following steps: performing state estimation according to a pre-constructed high-precision clock model and historical clock error data to obtain a clock state at each moment in a prediction interval; constructing a quadratic form cost function according to the clock state of each moment in the prediction interval and the weight matrix, minimizing the quadratic form cost function by adopting a rolling optimization method, outputting a control quantity of the current control moment, and optimizing the control quantity by utilizing a differential control quantity and a differential coefficient to obtain an optimal control quantity; obtaining a to-be-adjusted clock error sequence according to clock error data corresponding to a future moment in the prediction interval, performing phase adjustment on the to-be-adjusted clock error sequence according to the optimal control quantity of the current control moment and a time interval of two adjacent clock errors to obtain an adjusted clock error sequence, and iteratively updating the clock error sequence according to a time sequence to realize satellite-borne clock control. By adopting the method, the performance of the satellite-borne secondary frequency standard can be enhanced.

A method, apparatus and computer program product provide for frequency drift mitigation in a user equipment (UE). In the context of a method for mitigating frequency drift, the method modeling a base station clock with respect to a receiver clock so as to define the receiver clock at least partially based upon a frequency drift and a clock offset between the base station clock and the receiver clock to provide a floating frequency domain to compensate for the frequency drift between the base station clock and the receiver clock. The method also includes, based on modeling the base station clock with respect to the receiver clock, generating at least one timing offset of the receiver clock with respect to the base station clock. The method also includes determining a position of a UE associated with the receiver clock based at least partially upon the at least one timing offset.

A method, an apparatus, and a computer program product provide frequency drift mitigation in a user equipment (UE). In the context of a method for mitigating frequency drift, the method models a base station clock with respect to a receiver clock to define the receiver clock based at least in part on a frequency drift and a clock offset between the base station clock and the receiver clock to provide a floating frequency domain, therefore, the frequency drift between the base station clock and the receiver clock is compensated. The method further includes generating at least one timing offset of the receiver clock relative to the base station clock based on modeling the base station clock relative to the receiver clock. The method also includes determining a location of the UE associated with the receiver clock based at least in part on the at least one timing offset.

The invention discloses a dynamic clock domain switching method and device for an electronic price tag and a storage medium, and relates to the technical field of electronic price tags, and the dynamic clock domain switching method for the electronic price tag comprises the steps: determining that an external operation exists when a built-in NFC module of the electronic price tag detects that a radio frequency signal exists, and generating a wake-up signal based on the external operation; triggering a main chip of the electronic price tag to be switched from a sleep mode to a working mode based on the wake-up signal; determining an operation type of the external operation and a task type of a target task corresponding to the external operation according to the wake-up signal; determining a current time period type according to the current time and a preset variable price clock model; and according to the task type and the current time period type, determining a working module for executing the target task and a clock domain corresponding to each working module. In the application, the high and low frequency clocks or the sleep mode is switched according to the task demand, and the switching power consumption is reduced.

1. The name of the product of this design: Mobile power (clock style 2). 2. The purpose of this design product: to store electrical energy and provide power for mobile phones and other electronic products. 3. The design key point of this appearance design product lies in the shape. 4. The picture or photo that best illustrates the design points: three-dimensional picture.

The invention relates to the technical field of clock synchronization, in particular to a clock synchronization method based on a self-adaptive dynamic adjustment Kalman filter, which comprises the following steps of: defining a state vector containing clock skew and drift by adopting a second-order clock model, constructing a state transition and observation model, and calculating the state of the state transition and observation model; adaptively estimating a noise covariance based on a historical residual sliding window; measuring and predicting residual errors are recorded in each round of filtering, and the prediction residual errors are quantized; the residual error is stored in a sliding window, sample variance is calculated to obtain noise covariance initial estimation, and meanwhile, a simplified model of the proportional relation between clock skew and drift noise covariance is assumed; according to a covariance matching principle, using maximum likelihood estimation to calculate observation and process noise covariance from a sliding window residual error, that is, measuring a residual error square mean value as an observation noise covariance, presenting the process noise covariance in a matrix form, and accurately estimating noise characteristics; and performing exponential weighted moving average updating on the noise covariance by using a smoothing factor, performing Kalman filtering prediction and updating iteration to obtain clock skew and drifting optimal estimation, correcting a local clock according to the clock skew and drifting optimal estimation, and performing loop iteration to realize high-precision clock synchronization. According to the method, the noise covariance can be estimated and adjusted in real time, higher synchronization precision, higher convergence speed and higher robustness can be realized in a complex environment, and the problem that high-precision and stable clock synchronization is difficult to guarantee in a non-stable and high-dynamic wireless environment by the existing method is solved.

1. Name of the design product: clock model (square material box). 2. Use of the design product: used for loading different materials, can be used separately; suitable for educational props, children's toys. 3. Design points of the design product: the combination of shape and pattern. 4. Picture or photo that best indicates the design points: perspective drawing.

The invention relates to a distributed wireless network time synchronization method and device based on an enhanced clock model. The method comprises the following steps: constructing a network connection topological graph of a distributed wireless network; calculating a time difference and a frequency difference between each node and an adjacent node according to the enhanced clock model, performing state estimation according to the time difference and the frequency difference to obtain a time difference state vector and a frequency difference state vector, and obtaining a joint state vector according to the time difference state vector and the frequency difference state vector; constructing a system state transition equation and a system state observation equation of the combined state vector; performing iteration based on a Kalman filtering algorithm according to the system state transition equation and the system state observation equation to obtain optimal estimation values of time difference and frequency difference between each node and adjacent nodes, performing clock compensation and frequency compensation on the corresponding nodes according to the optimal estimation values, and iteratively updating the optimal estimation value at each moment. And time synchronization of the distributed wireless network is realized. By adopting the method, the time synchronization precision of the distributed wireless network can be improved.

The invention belongs to the technical field of civil aircraft flight control system verification, and particularly relates to a three-redundancy flight control system safety analysis method based on a timed automaton. Comprising the steps of determining a clock period and a random drift range of each component; the method comprises the following steps of: constructing a clock model by adopting a time automaton and a clock period and a random drift range of a component of a three-redundancy flight control system, wherein the modeling semantics of the time automaton comprises location, guard, invariant and channel; based on the architecture and the clock model of the three-redundancy flight control system, constructing a formal model of the three-redundancy flight control system based on the timed automaton; constructing a fault model on the basis of the formal model of the three-redundancy flight control system based on the timed automaton, wherein faults comprise crash, bus transmission and transient faults; performing safety analysis on the three-redundancy flight control system to obtain safety attributes based on the three-redundancy flight control system, and expressing the safety attributes as formalized protocols; and verifying whether the fault model meets the formalized specification or not by adopting a formalized verification tool.

1. The name of the product of this design: Mobile power (clock style 3). 2. The purpose of this design product: to store electrical energy and provide power for mobile phones and other electronic products. 3. The design key point of this appearance design product lies in the shape. 4. The picture or photo that best illustrates the design points: three-dimensional picture.

The invention relates to the technical field of circuits, in particular to a timing constraint text checking method and device and electronic equipment. Obtaining at least one initial time sequence constraint text corresponding to the target circuit; identifying each initial time sequence constraint text, and extracting clock information corresponding to at least one target clock included in the target circuit; generating an initial clock tree structure according to the clock information corresponding to each target clock; checking each target clock according to the initial clock tree structure, and determining an error type corresponding to the initial clock tree structure; and according to the error type, correcting the initial clock tree structure to generate a target clock tree structure. Finally, an accurate and compliant clock tree is obtained, a reliable clock model is provided for subsequent time sequence analysis and chip function verification, and design errors and iteration cost are reduced. Therefore, high efficiency and accuracy of SDC verification are realized.

The invention relates to a wireless communication time synchronization method supporting sleep, and belongs to the technical field of wireless sensor networks. The method comprises the following steps: firstly, aiming at the characteristic that wireless node equipment uses different types of clock oscillators in sleep and working states, establishing a clock model of a double-crystal-oscillator node; then, an indirect time synchronization mechanism is provided, and correction of sleep clock frequency offset and local clock phase offset is indirectly realized on the premise of correcting a working clock; when a plurality of double crystal oscillator nodes request synchronization at the same time, a reference node firstly completes correction of frequency offset and phase offset of a working clock of each to-be-synchronized node, then groups the nodes in pairs, takes the nodes as extended reference nodes in sequence, and completes correction of sleep clocks of each other based on an indirect time synchronization mechanism; and the rest of single nodes and the reference node directly finish correction of the sleep clock. According to the invention, the problem of difficulty in sleep clock synchronization of the double crystal oscillator nodes is solved, and the synchronization efficiency and synchronization precision of the large-scale double crystal oscillator nodes are improved.

The invention relates to the technical field of electronic design automation (EDA), specially relates to a method and a system for emulating IC design with an FPGA, and a storage medium. By identifying ports of sequential cells, the sequential cells are labeled as group A and group B according to the conditions that a data output of a sequential cell is connected to a user clock input of another sequential cell or is not connected to the user clock input of the other sequential cell but is connected to a data input of the other one sequential cell. All sequential cells in the group A is substituted with clock models[CA], and all sequential cells in the group B is substituted with clock models[CB]. The clock model[CA] and the clock model[CB] solve glitch problem by connecting glitch-containing user clock to a user enable non-sensitive to glitch. By configuring primary clocks′, each of the group A and the group B is driven by a primary clock′, thereby reducing numbers of clock domains, and the whole system can be simultaneously started-up and paused by controlling the primary clocks′.

The invention belongs to the technical field of wireless communication, and discloses a LoRa network synchronization method based on hardware time compensation modeling and a least square method, and the method comprises the following steps: S1, obtaining a bidirectional timestamp data set during message interaction between a gateway and a node; s2, performing data preprocessing on the obtained bidirectional timestamp data set; s3, in combination with hardware processing time delay, establishing a dynamic affine clock model to realize logic time synchronization; and S4, estimating the parameters by using a least square parameter estimation method, and verifying the prediction precision by using the estimated parameters obtained based on OLS in the step S5 and adopting a cross validation form. According to the LoRa network synchronization method based on hardware time compensation modeling and the least square method, node power consumption and hardware processing delay fluctuation are effectively reduced, and high-precision LoRa network time synchronization is achieved.

The invention relates to the technical field of electronic design automation (EDA), especially relates to a method and a system for emulating an IC design with an FPGA, and a storage medium. It is characterized by substituting clock models for the sequential cells; adding a user enable to an external port of a clock model compared to the port of a sequential cell in the IC design, through a user clock to which a user enable of a clock model is connected and a primary clock′ to which a clock input of a clock model is connected, a clock model[CA] reproducing the function of the sequential cell in the IC design by controlling outputting time of a data sample, and the clock model[CB] reproducing the function of the sequential cell in the IC design by controlling data sampling time; and configuring phase shifts for primary clocks' by which the clock model[CA] and the clock model[CB] are driven, so as to solve the technical problem of sampling error due to presence of the user clock while ensuring the functions of the original sequential cells.

The present application relates to a kind of wireless communication time synchronization method of sleep support, belong to wireless sensor network technical field.The method first for the characteristics of wireless node device in sleep and working state using different types of clock crystal oscillator, the clock model of double crystal oscillator node is established;Then there is indirect time synchronization mechanism, to correct working clock as premise, indirectly realize the correction of sleep clock frequency deviation and local clock phase deviation;When multiple double crystal oscillator nodes simultaneously request synchronization, reference node first completes the correction of each to be synchronized node working clock frequency deviation and phase deviation, then these nodes are grouped two by two, as extension reference node in turn, based on indirect time synchronization mechanism, complete the correction of each other sleep clock;For the remaining single node, directly with reference node complete the correction of sleep clock.The present application solves the problem of double crystal oscillator node sleep clock synchronization difficulty, improves large-scale double crystal oscillator node synchronization efficiency and synchronization accuracy.

A method, apparatus and computer program product provide for frequency drift mitigation in a user equipment (UE). In the context of a method for mitigating frequency drift, the method includes modeling a base station clock with respect to a receiver clock so as to define the receiver clock at least partially based upon a frequency drift and a clock offset between the base station clock and the receiver clock to provide a floating frequency domain to compensate for the frequency drift between the base station clock and the receiver clock (22). The method also includes, based on modeling the base station clock with respect to the receiver clock, generating at least one timing offset of the receiver clock with respect to the base station clock (24). The method also includes determining a position of a UE associated with the receiver clock based at least partially upon the at least one timing offset (26).

1. Name of the design product: Magnetic lamp clock model. 2. Use of the design product: Widely used and convenient and flexible, mainly for lighting. 3. Design key points of the design product: Lies in the shape. 4. Picture or photo that best shows the design key points: Three-dimensional view.

1. Name of the designed product: TT CARWATCH. 2. Use of the designed product: TT CARWATCH is used as a clock model placed on the center console of a car. 3. Design points of the designed product: the shape. 4. Picture or photo that best shows the design points: Fig. 1.

Techniques for clock manager monitoring for time sensitive networks are described. An apparatus, comprises a clock circuitry to manage a clock for a device, a processing circuitry coupled to the clock circuitry, the processing circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network, and a detector coupled to the processing circuitry and the clock circuitry, the detector to receive the clock manager control information, generate model control information based on a clock model, compare the clock manager control information with the model control information to generate difference information, and determine whether to generate an alert based on the difference information. Other embodiments are described and claimed.

The present invention relates to a timestamp-free synchronization clock parameter tracking method based on extended Kalman filter, and belongs to the technical field of wireless sensor networks. With a first order Gauss Markov model and a clock model as a state equation, evolution processes of clock skew and instantaneous clock offset is described. Then an observation equation constituted by observation models of timestamp-free synchronization and instantaneous clock offset is established, and clock skew and instantaneous clock offset are jointly tracked by a tracking method based on extended Kalman filter to realize synchronization between a node to be synchronized and a reference clock node. The method can track two time-varying parameters simultaneously by following a network data flow without needing a dedicated synchronization frame to exchange synchronization information, which reduces energy consumption and improves synchronization precision.

The present application relates to a distributed wireless network time synchronization method and device based on an enhanced clock model. The method includes: constructing a network connection topology graph of the distributed wireless network; calculating the time difference and frequency difference between each node and its adjacent nodes according to the enhanced clock model, performing state estimation based on the time difference and frequency difference to obtain a time difference state vector and a frequency difference state vector, obtaining a joint state vector according to the time difference state vector and the frequency difference state vector, and constructing a system state transition equation and a system state observation equation of the joint state vector; performing iteration based on the Kalman filtering algorithm according to the system state transition equation and the system state observation equation to obtain the optimal estimated values of the time difference and frequency difference between each node and its adjacent nodes, performing clock compensation and frequency compensation on the corresponding nodes according to the optimal estimated values, and iteratively updating the optimal estimated values at each moment to achieve time synchronization of the distributed wireless network. Using this method can improve the time synchronization accuracy of the distributed wireless network.