11 results about "Clock model" patented technology

The invention discloses a dynamic clock domain switching method and device for an electronic price tag and a storage medium, and relates to the technical field of electronic price tags, and the dynamic clock domain switching method for the electronic price tag comprises the steps: determining that an external operation exists when a built-in NFC module of the electronic price tag detects that a radio frequency signal exists, and generating a wake-up signal based on the external operation; triggering a main chip of the electronic price tag to be switched from a sleep mode to a working mode based on the wake-up signal; determining an operation type of the external operation and a task type of a target task corresponding to the external operation according to the wake-up signal; determining a current time period type according to the current time and a preset variable price clock model; and according to the task type and the current time period type, determining a working module for executing the target task and a clock domain corresponding to each working module. In the application, the high and low frequency clocks or the sleep mode is switched according to the task demand, and the switching power consumption is reduced.

The invention relates to the technical field of clock synchronization, in particular to a clock synchronization method based on a self-adaptive dynamic adjustment Kalman filter, which comprises the following steps of: defining a state vector containing clock skew and drift by adopting a second-order clock model, constructing a state transition and observation model, and calculating the state of the state transition and observation model; adaptively estimating a noise covariance based on a historical residual sliding window; measuring and predicting residual errors are recorded in each round of filtering, and the prediction residual errors are quantized; the residual error is stored in a sliding window, sample variance is calculated to obtain noise covariance initial estimation, and meanwhile, a simplified model of the proportional relation between clock skew and drift noise covariance is assumed; according to a covariance matching principle, using maximum likelihood estimation to calculate observation and process noise covariance from a sliding window residual error, that is, measuring a residual error square mean value as an observation noise covariance, presenting the process noise covariance in a matrix form, and accurately estimating noise characteristics; and performing exponential weighted moving average updating on the noise covariance by using a smoothing factor, performing Kalman filtering prediction and updating iteration to obtain clock skew and drifting optimal estimation, correcting a local clock according to the clock skew and drifting optimal estimation, and performing loop iteration to realize high-precision clock synchronization. According to the method, the noise covariance can be estimated and adjusted in real time, higher synchronization precision, higher convergence speed and higher robustness can be realized in a complex environment, and the problem that high-precision and stable clock synchronization is difficult to guarantee in a non-stable and high-dynamic wireless environment by the existing method is solved.

The invention relates to the technical field of circuits, in particular to a timing constraint text checking method and device and electronic equipment. Obtaining at least one initial time sequence constraint text corresponding to the target circuit; identifying each initial time sequence constraint text, and extracting clock information corresponding to at least one target clock included in the target circuit; generating an initial clock tree structure according to the clock information corresponding to each target clock; checking each target clock according to the initial clock tree structure, and determining an error type corresponding to the initial clock tree structure; and according to the error type, correcting the initial clock tree structure to generate a target clock tree structure. Finally, an accurate and compliant clock tree is obtained, a reliable clock model is provided for subsequent time sequence analysis and chip function verification, and design errors and iteration cost are reduced. Therefore, high efficiency and accuracy of SDC verification are realized.

The invention belongs to the technical field of wireless communication, and discloses a LoRa network synchronization method based on hardware time compensation modeling and a least square method, and the method comprises the following steps: S1, obtaining a bidirectional timestamp data set during message interaction between a gateway and a node; s2, performing data preprocessing on the obtained bidirectional timestamp data set; s3, in combination with hardware processing time delay, establishing a dynamic affine clock model to realize logic time synchronization; and S4, estimating the parameters by using a least square parameter estimation method, and verifying the prediction precision by using the estimated parameters obtained based on OLS in the step S5 and adopting a cross validation form. According to the LoRa network synchronization method based on hardware time compensation modeling and the least square method, node power consumption and hardware processing delay fluctuation are effectively reduced, and high-precision LoRa network time synchronization is achieved.

The present invention relates to a timestamp-free synchronization clock parameter tracking method based on extended Kalman filter, and belongs to the technical field of wireless sensor networks. With a first order Gauss Markov model and a clock model as a state equation, evolution processes of clock skew and instantaneous clock offset is described. Then an observation equation constituted by observation models of timestamp-free synchronization and instantaneous clock offset is established, and clock skew and instantaneous clock offset are jointly tracked by a tracking method based on extended Kalman filter to realize synchronization between a node to be synchronized and a reference clock node. The method can track two time-varying parameters simultaneously by following a network data flow without needing a dedicated synchronization frame to exchange synchronization information, which reduces energy consumption and improves synchronization precision.

This invention relates to the field of radio direction finding technology, specifically to an enhanced BeiDou precise time synchronization method based on a receiver clock model. The method includes: acquiring multi-source data and preprocessing it; establishing a BeiDou receiver clock model, optimizing model parameters using the least squares method, outputting a first clock drift value and a first coefficient, and using a machine learning model to predict a second clock drift value and a second coefficient; then, using a Bayesian fusion model to combine the BeiDou receiver clock model and the machine learning model to output a predicted clock drift value and calculate a predicted time offset value; calculating the carrier-to-noise ratio loss value, autocorrelation function distortion value, and phase change value to generate signal quality indicators, and using a weighted allocation mechanism to calculate an error compensation value; finally, correcting the clock deviation based on the error compensation value. This invention improves the accuracy of clock drift prediction and effectively corrects clock deviation by combining multiple models, thereby improving the accuracy of time synchronization in mountainous areas.

The present application relates to the technical field of traveling wave signal sampling, and particularly relates to a power line traveling wave fault positioning method, system and device based on multi-channel clock synchronization and a storage medium. A high-precision synchronous clock model is established based on satellite clock and crystal oscillator clock correction technology. Signals of the single high-precision synchronous clock model are accurately distributed to multiple ADC devices, so that strict synchronization of the multi-channel sampling clock can be ensured, to avoid the situation that the time data of the initial traveling wave reaching the measurement end is erroneous due to low synchronization of the built-in clock of different ADC devices. Then, by combining the running state data and signal transmission state data of each ADC device in the running process, the data is further corrected, so that the reliability and accuracy of the data are further improved, so that errors in the calculation of the distance between the fault point and the measurement point are avoided, and the accuracy of fault positioning is improved.

The application relates to a particle filtering-based time-stamp-free synchronization clock parameter tracking method and belongs to the technical field of wireless sensor networks.The method comprises the following steps: S1, establishing a state equation according to a first-order Gauss Markov model and a clock model, and then establishing an observation equation according to an observation model of clock instantaneous offset in combination with time-stamp-free synchronization; and S2, utilizing an adaptive Gauss mixed extended Kalman particle filtering algorithm to jointly track clock frequency deviation and clock phase deviation, so that clock synchronization between a to-be-synchronized node and a clock reference node under arbitrary random time delay is realized.The application considers the diversity of random time delay models, utilizes an improved particle filtering algorithm to jointly track clock synchronization parameters, is robust to arbitrary random time delay, is more in line with actual application scenarios, and does not need to transmit any time stamp in the whole clock synchronization parameter tracking process, so that the energy consumption of nodes is significantly reduced.

A method, apparatus and computer program product provide for frequency drift mitigation in a user equipment (UE). In the context of a method for mitigating frequency drift, the method modeling a base station clock with respect to a receiver clock so as to define the receiver clock at least partially based upon a frequency drift and a clock offset between the base station clock and the receiver clock to provide a floating frequency domain to compensate for the frequency drift between the base station clock and the receiver clock. The method also includes, based on modeling the base station clock with respect to the receiver clock, generating at least one timing offset of the receiver clock with respect to the base station clock. The method also includes determining a position of a UE associated with the receiver clock based at least partially upon the at least one timing offset.

1. Name of the product in this design: Earplugs (Clock Model). 2. Purpose of this design: for use as an earplug worn on the ear to isolate sound. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the key design points: Design 1 3D view. 5. Design 1 is designated as the basic design.

A multifunctional clock model comprises an upper cover shell, a middle shell and a lower shell from top to bottom, and is technically characterized in that the upper cover shell, the middle shell and the lower shell are sequentially clamped to form a cylinder; a clock model is arranged at the upper part of the upper cover shell and comprises an hour hand and a minute hand which can rotate around the center; a hollow cylinder a for clamping is arranged at the lower part of the upper cover shell; the upper portion of the middle shell is provided with a hollow column body b used for being connected with the hollow column body a in a clamped mode, a baffle is further arranged in the hollow column body b to form a cavity I, and the lower portion of the middle shell is provided with a hollow column body c used for being connected with the hollow column body b or the lower shell in a clamped mode. A hollow cylinder d for clamping the hollow cylinder a or the hollow cylinder c is arranged at the upper part of the lower shell, and a cavity II is formed in the hollow cylinder d; and seal bodies are arranged in the cavity I and the cavity II.