6 results about "Clock model" patented technology

The invention discloses a dynamic clock domain switching method and device for an electronic price tag and a storage medium, and relates to the technical field of electronic price tags, and the dynamic clock domain switching method for the electronic price tag comprises the steps: determining that an external operation exists when a built-in NFC module of the electronic price tag detects that a radio frequency signal exists, and generating a wake-up signal based on the external operation; triggering a main chip of the electronic price tag to be switched from a sleep mode to a working mode based on the wake-up signal; determining an operation type of the external operation and a task type of a target task corresponding to the external operation according to the wake-up signal; determining a current time period type according to the current time and a preset variable price clock model; and according to the task type and the current time period type, determining a working module for executing the target task and a clock domain corresponding to each working module. In the application, the high and low frequency clocks or the sleep mode is switched according to the task demand, and the switching power consumption is reduced.

The invention relates to the technical field of circuits, in particular to a timing constraint text checking method and device and electronic equipment. Obtaining at least one initial time sequence constraint text corresponding to the target circuit; identifying each initial time sequence constraint text, and extracting clock information corresponding to at least one target clock included in the target circuit; generating an initial clock tree structure according to the clock information corresponding to each target clock; checking each target clock according to the initial clock tree structure, and determining an error type corresponding to the initial clock tree structure; and according to the error type, correcting the initial clock tree structure to generate a target clock tree structure. Finally, an accurate and compliant clock tree is obtained, a reliable clock model is provided for subsequent time sequence analysis and chip function verification, and design errors and iteration cost are reduced. Therefore, high efficiency and accuracy of SDC verification are realized.

The present invention relates to a timestamp-free synchronization clock parameter tracking method based on extended Kalman filter, and belongs to the technical field of wireless sensor networks. With a first order Gauss Markov model and a clock model as a state equation, evolution processes of clock skew and instantaneous clock offset is described. Then an observation equation constituted by observation models of timestamp-free synchronization and instantaneous clock offset is established, and clock skew and instantaneous clock offset are jointly tracked by a tracking method based on extended Kalman filter to realize synchronization between a node to be synchronized and a reference clock node. The method can track two time-varying parameters simultaneously by following a network data flow without needing a dedicated synchronization frame to exchange synchronization information, which reduces energy consumption and improves synchronization precision.

The present application relates to the technical field of traveling wave signal sampling, and particularly relates to a power line traveling wave fault positioning method, system and device based on multi-channel clock synchronization and a storage medium. A high-precision synchronous clock model is established based on satellite clock and crystal oscillator clock correction technology. Signals of the single high-precision synchronous clock model are accurately distributed to multiple ADC devices, so that strict synchronization of the multi-channel sampling clock can be ensured, to avoid the situation that the time data of the initial traveling wave reaching the measurement end is erroneous due to low synchronization of the built-in clock of different ADC devices. Then, by combining the running state data and signal transmission state data of each ADC device in the running process, the data is further corrected, so that the reliability and accuracy of the data are further improved, so that errors in the calculation of the distance between the fault point and the measurement point are avoided, and the accuracy of fault positioning is improved.

1. Name of the product in this design: Earplugs (Clock Model). 2. Purpose of this design: for use as an earplug worn on the ear to isolate sound. 3. The key design feature of this product is its shape. 4. The image or photograph that best illustrates the key design points: Design 1 3D view. 5. Design 1 is designated as the basic design.

A multifunctional clock model comprises an upper cover shell, a middle shell and a lower shell from top to bottom, and is technically characterized in that the upper cover shell, the middle shell and the lower shell are sequentially clamped to form a cylinder; a clock model is arranged at the upper part of the upper cover shell and comprises an hour hand and a minute hand which can rotate around the center; a hollow cylinder a for clamping is arranged at the lower part of the upper cover shell; the upper portion of the middle shell is provided with a hollow column body b used for being connected with the hollow column body a in a clamped mode, a baffle is further arranged in the hollow column body b to form a cavity I, and the lower portion of the middle shell is provided with a hollow column body c used for being connected with the hollow column body b or the lower shell in a clamped mode. A hollow cylinder d for clamping the hollow cylinder a or the hollow cylinder c is arranged at the upper part of the lower shell, and a cavity II is formed in the hollow cylinder d; and seal bodies are arranged in the cavity I and the cavity II.