Clock model implementation method and device, computer equipment and storage medium

Abstract

The invention relates to a clock model implementation method and device, computer equipment and a storage medium. The method comprises the following steps: setting a clock generation component for generating a clock; obtaining a test case; generating a clock generation mode according to the test case, and adding the clock generation mode into a clock generation component to generate a corresponding clock by the clock generation component; and transmitting the clock to the top layer of the verification environment in an interface mode, and performing clock verification with the to-be-verified module by adopting the clock. According to the invention, the clock generation assembly is independent of the top layer of the verification environment; a corresponding clock generation mode is generated according to the test case, and the clock generation assembly calls a clock generation mode by adopting a callback mechanism, generates a corresponding clock, and transmits the clock to the top layer of the verification environment by utilizing an interface to perform clock verification on the to-be-verified module, so that the code maintenance of the top layer of the verification environment is simplified, the clock scene is controllable and more flexible, and the maintenance is clearer.

Description

technical field [0001] The present invention relates to a clock generation method, more specifically to a clock model realization method, device, computer equipment and storage medium. Background technique [0002] In the module-level verification process of the chip, the clock signal is usually generated by the verification environment instead of using a real PLL (Phase Locked Loop). One can eliminate the PLL configuration process; Only care about the functional correctness of the module itself, and don't care whether the system-level PLL can work normally. Generally, the module-level verification environment implements the clock generation function at the top layer of the verification environment, which is often generated using the procedural statements initial and always syntax of verilog or system verilog. The clock generated in this way is often less flexible, and it is difficult to directly meet the requirements of various clock frequency scenarios; in addition, becau...

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Problems solved by technology

Using this method will complicate clk_gen with the increase of clock scenarios, and the clock scenarios that need to be maintained will not be clear enough; in addition, since test cases are completely independent from clk_gen, if you want to implement clock scenarios that change dynamically with test cases, It needs to pass the signal, and it can be realized by shaking hands between the test case and clk_gen, which is troublesome and not flexible enough.

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