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Microprocessing device having programmable waist states

A waiting state, micro-processing technology, applied in the direction of electrical digital data processing, instruments, calculations, etc., can solve the problem of CPU clock cycle extension and other issues

Inactive Publication Date: 2003-09-03
ATMEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

During a read access request from the CPU section to the storage device, the period of the CPU clock supplied to the CPU section is extended

Method used

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  • Microprocessing device having programmable waist states
  • Microprocessing device having programmable waist states
  • Microprocessing device having programmable waist states

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Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0018] Referring to FIG. 1 , data processing system 100 of the present invention includes a variety of various subsystems arranged around system bus 120 . Microprocessing unit 110 , such as a microcontroller or the like, includes core logic 112 and internal memory 114 . The internal clock 156 provides the clock signal s130 to the driver micro-processing unit 110 . Data transfers between core logic 112 and memory 114 occur over internal bus 116 . The internal bus is connected to the system bus 120 to provide data transmission to the outside of the micro-processing unit 110 . Exiting the bus 116 is a memory address line s140 to a memory controller 152 . The core logic 112 provides a data selection signal s142, indicating that the core needs data transfer (read or write). In particular, signal s142 HI indicates a data transfer cycle, and signal s142 LO indicates an address cycle. The data selection signal is sent to the storage controller 152 and the wait state generator 160 ...

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PUM

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Abstract

The present invention deals with the control of a data bus (120) by a microcontroller (110), taking into account the fact that memory output drivers require a finite amount of time to electrically release the bus after an output operation. Each memory (130, 132) has an associated wait state number for selectively placing the microcontroller (110) in a wait state of variable length subsequent to a read operation and prior to the next I / O operation.

Description

(1) Technical field [0001] The present invention relates to microprocessing devices, and more particularly to a programmable wait state scheme for I / O with external devices. (2) Background technology [0002] Generally, whenever data is exchanged between two devices in the same system (for example: a microprocessor unit and a memory device), the system must verify that the interaction between the two devices must be synchronized. For example, more recently, technologies that allow high-speed operation have been used in the manufacture of microprocessors and microcontrollers. Clock speeds of 300MHz or higher have become commonplace. However, peripheral devices, especially storage devices such as flash memory (FLASH), static access memory (SRAM), and electrically erasable read-only memory (EEPROM), usually do not have such a high clock speed. [0003] A common method of synchronizing with slow devices is through the use of wait states to vary the duration of the bus cycle fo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/30G06F12/00G06F13/18G06F13/42
CPCG06F13/4243G06F13/18
Inventor M·奥勒斯
Owner ATMEL CORP