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Clock synchronization method, circuit and logic device applicable to jesd204b protocol

A technology of clock synchronization and equipment, which is applied in the field of signal processing, can solve problems such as poor reliability, limited performance, and low synchronization efficiency, and achieve the effects of high reliability, improved synchronization efficiency, and strong compatibility

Active Publication Date: 2021-10-08
牛芯半导体(深圳)有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The purpose of this application is to provide a clock synchronization method, circuit and logic device suitable for the JESD204B protocol, at least to a certain extent, to overcome technical problems such as the need for multiple synchronizations, poor reliability, limited performance, and low synchronization efficiency in related technologies

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  • Clock synchronization method, circuit and logic device applicable to jesd204b protocol
  • Clock synchronization method, circuit and logic device applicable to jesd204b protocol
  • Clock synchronization method, circuit and logic device applicable to jesd204b protocol

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Embodiment Construction

[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concepts of example embodiments to those skilled in the art.

[0065] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the application. However, those skilled in the art will appreciate that the technical solutions of the present application may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed. In other instances, well-known methods,...

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Abstract

This application belongs to the technical field of signal processing, and specifically relates to a clock synchronization method, circuit and logic device applicable to the JESD204B protocol; The reference signal generates the nth device clock signal, and generates the nth reference signal at the same time as the nth device clock signal; the reference signal of the latter stage of the application is automatically generated according to multiple clock synchronization circuits, and no external input is required. The reference signal is used to adjust the clock phase of the subsequent stage, which greatly improves the synchronization efficiency, high reliability, strong compatibility, and easy to use.

Description

technical field [0001] The application belongs to the technical field of signal processing, and in particular relates to a clock synchronization method, circuit and logic device applicable to the JESD204B protocol. Background technique [0002] The rapid development of 5G and Internet of Things technology has brought massive data exchange, making the data throughput more and more large, especially for ADC / DAC above 500MSPS, and JESD204B is the third generation standard of JEDEC (Solid State Technology Association), Its link rate reaches 12.5Gb / s and has the advantages of less board space required for data interface, lower setup and hold timing requirements, and smaller packages for converters and logic devices. [0003] The JESD204B protocol has deterministic delay requirements, therefore, the phase adjustment of the clock circuit is required. However, the adjustment of the clock phase by the existing clock circuit or clock synchronization method will affect the stability o...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04J3/06
CPCH04J3/0638
Inventor 李长松
Owner 牛芯半导体(深圳)有限公司