Clock synchronization method and circuit suitable for JESD204B protocol and logic equipment
A clock synchronization and equipment technology, applied in the field of signal processing, can solve the problems of limited performance, low synchronization efficiency, poor reliability, etc., and achieve the effect of improving synchronization efficiency, strong compatibility, and high reliability
Active Publication Date: 2021-08-24
牛芯半导体(深圳)有限公司
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[0005] The purpose of this application is to provide a clock synchronization method, circuit and logic device suitable for the JESD204B protocol, at least to a certain extent, to overcome technical problems such as the need for multiple synchronizations, poor reliability, limited performance, and low synchronization efficiency in related technologies
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[0064] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the concepts of example embodiments to those skilled in the art.
[0065] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the application. However, those skilled in the art will appreciate that the technical solutions of the present application may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed. In other instances, well-known methods,...
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The invention belongs to the technical field of signal processing, and particularly relates to a clock synchronization method and circuit suitable for a JESD204B protocol and logic equipment. The method comprises the steps: generating an n-th equipment clock signal according to the clock frequency of the n-th equipment clock signal, the (n-1)-th equipment clock signal and the (n-1)-th reference signal, and generating the n-th reference signal while generating the n-th equipment clock signal. According to the invention, the reference signal of the post-stage is automatically generated according to the plurality of clock synchronization circuits, a new reference signal does not need to be additionally input from the outside to adjust the clock phase of the post-stage, the synchronization efficiency is greatly improved, the reliability is high, the compatibility is strong, and the use is convenient.
Description
technical field [0001] The application belongs to the technical field of signal processing, and in particular relates to a clock synchronization method, circuit and logic device applicable to the JESD204B protocol. Background technique [0002] The rapid development of 5G and Internet of Things technology has brought massive data exchange, making the data throughput more and more large, especially for ADC / DAC above 500MSPS, and JESD204B is the third generation standard of JEDEC (Solid State Technology Association), Its link rate reaches 12.5Gb / s and has the advantages of less board space required for data interface, lower setup and hold timing requirements, and smaller packages for converters and logic devices. [0003] The JESD204B protocol has deterministic delay requirements, therefore, the phase adjustment of the clock circuit is required. However, the adjustment of the clock phase by the existing clock circuit or clock synchronization method will affect the stability o...
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IPC IPC(8): H04J3/06
CPCH04J3/0638
Inventor 李长松
Owner 牛芯半导体(深圳)有限公司