Method, equipment and medium for realizing data parity rearrangement

Abstract

The embodiment of the invention relates to a method and equipment for realizing data parity rearrangement and a medium, and the method comprises the steps: determining a first mapping parameter based on the thread count of a thread group; based on the first mapping parameter, mapping data of the first register to the third register and mapping data of the second register to a fourth register; shifting data of the first register, the second register, the third register and the fourth register to a transfer register; based on the address of the transfer register, executing extraction on the data in the transfer register so as to obtain first data, second data, third data and fourth data; first data and second data are written into the first register and the second register respectively, and therefore register data odd-even rearrangement is achieved. Therefore, odd-even rearrangement of the data between the two registers can be realized more quickly under the condition that the address of the shared memory is not calculated.

Description

technical field [0001] Embodiments of the present disclosure generally relate to the field of processors, and more particularly, to a method, computing device, and computer-readable storage medium for implementing data parity rearrangement. Background technique [0002] In general, in general-purpose computing on graphics processing units (GPGPU), a fast Fourier (FFT) operation is usually involved in which the input is a real number and the output is a complex number (R2C). The operation requires parity rearrangement of the original input sequence of real numbers to reassemble into a new sequence of complex numbers. This involves parity reordering of data between thread groups (wraps) between different registers. The parity rearrangement operation relies on data interaction between thread groups. [0003] The existing way of data interaction between thread groups is mainly through shared memory. The system first calculates the corresponding shared memory address according...

AI Technical Summary

Problems solved by technology

This method increases the read delay of the instruction and wastes the data bandwidth of the instruction memory.

In addition, the index calculation of the shared memory is more complex and needs to be converted into additional calculations for the corresponding addresses

[0004] To sum up, the disadvantages of the traditional schemes for data parity rearrangement are: the addition of complex shared memory index address conversion calculation operations, and the long delay of read and write operations in the shared memory, which affects the program performance

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