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Bonding wire arrangement structure of semiconductor chip package

A technology of chip packaging and wire bonding, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc.

Active Publication Date: 2005-03-16
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, in some semiconductor chips, there are not enough ground lines to isolate noise or prevent inductive coupling between signals, so other lines must be used to do the job

Method used

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  • Bonding wire arrangement structure of semiconductor chip package
  • Bonding wire arrangement structure of semiconductor chip package
  • Bonding wire arrangement structure of semiconductor chip package

Examples

Experimental program
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no. 1 Embodiment

[0026] read on Figure 1A The bonding pads on the semiconductor chip 11 are connected to the corresponding pins 50 on the packaging substrate 100 via bonding wires, so that the electronic components on the semiconductor chip can transmit signals and supply power through the packaging substrate 100 . According to the first embodiment of the present invention, the pins 50 on the package substrate 100 are arranged on the same straight line, and the pins 50 connected to the power supply pads are connected to the package substrate 100 through the internal wiring of the package substrate. 31 on the power ring.

[0027] see Figure 1B , this picture is Figure 1A The cross-sectional view of line AA' shows the arrangement of bonding wires. Through the arrangement of bonding pads on the semiconductor chip 11, the arrangement of bonding wires will be the same as that of each group of differential signal bonding wires (such as S1+ and S1-). The two sides are respectively adjacent to a p...

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Abstract

A structural arrangement of bonding wire in seal agent of semiconductor chip, includes: at least two a bonding wire for signal which is connected to a seal substrate by a chip; at least two bonding wire for power source which are ranged on the two sides of the bonding wire for signal, using the bonding wire for power source surrounding bonding wire of differential signal or the common bonding wire for signal, to make the bonding wire for signal acquire more screen protection.

Description

technical field [0001] The invention relates to a semiconductor chip packaging structure, in particular to a bonding wire arrangement structure of a semiconductor chip packaging body. Background technique [0002] The purpose of electronic packaging can be summarized as transmitting electric energy, transmitting circuit signals, providing heat dissipation and structural protection and support. If the chip is regarded as the brain in the human body, then various circuit parts can be regarded as various organs inside the human body, and the electronic package is like a muscle skeleton composed of these organs, and the online circuits in the package are like blood vessels and nerves. It provides a path for energy and circuit signal transmission, so that the function of the electronic product formed after the chip and various circuit components are packaged can be exerted. As electronic products continue to introduce new ones in terms of operating frequency and performance, pac...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/60H01L23/48
CPCH01L2924/01015H01L2924/01006H01L2924/01082H01L2924/3011H01L2224/49431H01L2224/49433H01L2224/49175H01L2924/30107H01L2924/3025H01L24/49H01L2224/48227H01L24/06H01L2224/05554H01L2224/49H01L2924/30111H01L2924/00012H01L2924/00
Inventor 谢佳容陈俊宏
Owner VIA TECH INC
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