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Buffer switch and scheduling method thereof

A scheduling method and switching technology, applied in data exchange details, time-division multiplexing selection devices, transmission systems, etc., can solve problems such as high-speed operation difficulties and operational difficulties

Inactive Publication Date: 2005-08-03
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there is still a problem that high-speed operation is difficult because a probability function must be used in the steps of sending authorization and sending acceptance
[0026] However, there is still a problem with such a SLIP scheme: synchronous phenomenon occurs, that is, several output ports authorize the same input port
Namely, there is a problem that high-speed operation becomes difficult when the number of input ports / output ports increases
The 2DRR algorithm is difficult to operate at high speeds because the number of steps required to execute the algorithm also increases with the number of input and output ports

Method used

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Embodiment Construction

[0068] Preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings, so that those of ordinary skill in the art to which the present invention pertains can easily implement the present invention.

[0069] figure 1 Operation of a typical 4x4 switch is represented, where the data 110a-110d input to the corresponding input port includes the destination port number(s).

[0070] exist figure 1 , the reference time data 110a input to input port 1 has a destination port number of 1, the reference time data 110b input to input port 2 has a destination port number of 3, and the reference time data 110c input to input port 3 has a destination port number of Number 3, the reference time data 110d input to input port 4 has destination port number 1.

[0071] At this time, a parallel iterative matching (PIM) scheme is used, which is a typical scheme of the path establishment algorithm. Since the different output ports 2 110b an...

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Abstract

In a buffer switch and scheduling method thereof, conflict sensing and random selection logic configuration are not required. The buffer switch comprises: input buffer units for converting serial data inputted from respective input ports to parallel data; shift and comparison units for comparing currently stored data to parallel data aligned by the input buffer units, for determining paths to output the data depending on data validity, and for calculating a gating time needed to forward the data; output buffer units for outputting the data received via the input ports at the same speed as the speed at reception; a switching unit for gating paths between the shift and comparison units and the output buffer units; and a control unit for establishing the paths by enabling the input buffer units and the output buffer units for the gating time of relevant buffers depending on the establishment paths and the gating time from the shift and comparison unit.

Description

technical field [0001] The present invention relates to a buffer switch and a scheduling method thereof, in particular, the present invention relates to a buffer switch and a scheduling method thereof in which conflict detection and random selection logic configuration are not required. Background technique [0002] In order to provide various services on an integrated service network, a series of researches have been carried out in the past ten years. [0003] In particular, many scheduling schemes have been proposed to ensure that users who have signed a service contract have a frequency band and a delay, and there will be no traffic drop that does not meet the service contract. [0004] For example, there is a work-saving scheme that consumes no time while the unit still exists. Work-saving schemes include: "virtual clock", "delayed-EDD (earliest suitable date)", "WFQ (weighted fair queuing)", "WF2Q (worst case fair weighted fair queuing)", "SCFQ (since Clocks line up r...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/02H04L12/28H04L12/54H04L12/56H04Q11/04
CPCH04L49/254H04L49/3045H04L49/101H04L49/252E03B7/12E04H1/1216
Inventor 崔英崔炳求金善琦
Owner SAMSUNG ELECTRONICS CO LTD