Pseudo-random bit sequence (PRBS) synchronization for interconnects with dual-tap scrambling devices
a technology of synchronizing interconnects and random bits, applied in the direction of securing communication, digital transmission, instruments, etc., can solve the problems of large amount of unwanted intersymbol interference (isi) in the data transmission system of chip carriers, and long cycl
Inactive Publication Date: 2009-10-08
INT BUSINESS MASCH CORP
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Problems solved by technology
One problem of particular concern to communication systems having data rates in the Gbit / s range is that the printed wires of a printed circuit board (PCB) backplane or the lossy transmission lines of a ceramic multi-chip carrier introduces large amounts of unwanted intersymbol interference (ISI) in the data transmission system.
However, an LFSR with a well-chosen feedback function can produce a sequence of bits which appears random and which has a very long cycle.
Method used
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[0036]Reference will now be made to various embodiments, examples of which are illustrated in the accompanying drawings. However, these various exemplary embodiments are not intended to limit the disclosure. On the contrary, the disclosure is intended to cover alternatives, modifications, and equivalents.
[0037]Throughout the application, description of various embodiments may use “comprising” language, however, it will be understood by one of skill in the art, that in some specific instances, an embodiment can alternatively be described using the language “consisting essentially of” or “consisting of.”
[0038]For purposes of better understanding the present teachings and in no way limiting the scope of the teachings, it will be clear to one of skill in the art that the use of the singular includes the plural unless specifically stated otherwise. Therefore, the terms “a,”“an” and “at least one” are used interchangeably in this application.
[0039]As will be appreciated by one skilled in ...
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A system for synchronizing interconnects in a link system according to various embodiments can include a computer configured to receive input data at a transmit side, the transmit side including at least one pseudo-random bit sequence scrambler; scramble the input data at the transmit side via the pseudo-random bit scrambler with dual tap sequences resulting in scrambled data; transmit the scrambled data with the dual tap sequences along all lanes of a plurality of lanes to a receive side via a bus interconnecting the plurality of lanes, the receive side including at least one pseudo-random bit sequence descrambler, and the receive side directly connected to the transmit side via the bus; synchronize the at least one pseudo-random bit sequence scrambler to the at least one pseudo-random bit sequence descrambler; and de-scramble the transmitted scrambled data at the receive side resulting in the input data.
Description
[0001]This application is a continuation application of U.S. patent application Ser. No. 12 / 098,878, filed Apr. 7, 2008, which is hereby incorporated by reference.FIELD[0002]The present teachings relate to devices and methods for pseudo-random bit sequence (PRBS) synchronization for interconnects with dual-tap scrambling.INTRODUCTION[0003]In wire-based communication systems, information additional to the system data is typically queued up and transmitted in series with the system data as bandwidth permits. One problem of particular concern to communication systems having data rates in the Gbit / s range is that the printed wires of a printed circuit board (PCB) backplane or the lossy transmission lines of a ceramic multi-chip carrier introduces large amounts of unwanted intersymbol interference (ISI) in the data transmission system.[0004]One conventional method employed to reduce ISI introduced timing jitter is based on coding or scrambling of the data stream to guarantee that no long...
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IPC IPC(8): H04L9/22
CPCG06F13/4234
Inventor BUCHMANN, PETERSCHMATZ, MARTIN LEO
Owner INT BUSINESS MASCH CORP