Equalized rise and fall slew rates for a buffer

Abstract

Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a slew reference based on at least one of the rise slew rate or the fall slew rate at the input of the buffer; comparing the rise slew rate and the fall slew rate at the output of the buffer to the slew reference; and generating at least one of a rise control signal or a fall control signal for adjusting at least one of the rise slew rate or the fall slew rate at the output of the buffer.

Description

BACKGROUND OF THE INVENTION[0001]The subject matter disclosed herein relates generally to integrated circuits. More specifically, the disclosure provided herein relates to a method and structure for equalizing rise and fall slew rates for a buffer.[0002]The rise and fall slew rate (transitions) of a clocking signal can affect the switching threshold of a transistor's operation in circuits. A mismatched rise and fall slew rate can lead to undesired duty cycle propagation for the clock signal through critical paths. For example, with input / output drivers and phase interpolators, a mismatched rise and fall slew rate can lead to timing errors and unwanted results.BRIEF DESCRIPTION OF THE INVENTION[0003]Aspects of the invention provide for equalizing rise and fall slew rates at an output for a buffer. In one embodiment, a method includes: measuring, simultaneously, rise and fall slew rates at an input of the buffer and rise and fall slew rates at the output of the buffer; generating a sl...

AI Technical Summary

Benefits of technology

This patent describes a method and system for equalizing the rate at which an output buffer increases or decreases its signal. This involves measuring the rates at which the input buffer is increasing or decreasing its signal, and comparing them to a reference rate. Based on the results of this comparison, the system generates control signals to adjust the rate at which the output buffer increases or decreases its signal. The technical effect of this invention is that it helps to ensure the smooth and accurate transition of signals through the buffer, which can lead to improved overall performance and reliability.

Problems solved by technology

A mismatched rise and fall slew rate can lead to undesired duty cycle propagation for the clock signal through critical paths.

For example, with input / output drivers and phase interpolators, a mismatched rise and fall slew rate can lead to timing errors and unwanted results.

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