Optimized testing of a partially symmetric quantum-logic circuit

a quantum logic and circuit technology, applied in the field of optimizing testing of a partially symmetric quantum, can solve the problems of prohibitively expensive or resource-intensive testing of a q-module comprising a larger number of inputs and states

Active Publication Date: 2017-12-28
KYNDRYL INC
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Problems solved by technology

Testing a q-module comprising larger numbers of inputs and states can therefore be prohibitively expensive or resource-intensive.

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  • Optimized testing of a partially symmetric quantum-logic circuit
  • Optimized testing of a partially symmetric quantum-logic circuit
  • Optimized testing of a partially symmetric quantum-logic circuit

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Embodiment Construction

[0035]Embodiments of the present invention optimize the operation of a test system or test application that verifies correct operation of a partially symmetric quantum-logic circuit.

[0036]Testing a quantum-logic circuit (or “q-module”) can be far more time-consuming and resource-intensive than testing conventional binary logic circuits because quantum logic is not limited to two states. Where verifying operation of a two-input binary AND circuit would require four tests, corresponding to four possible binary inputs {00, 01, 10, and 11}, a two-input q-module that supports four states A, B, C, and D, would require 16 tests to test 16 possible input states {AA, AB, AC, AD, BA, BB, BC, BD, CA, CB, CC, CD, DA, DB, DC, and DD}. Embodiments of the present invention solve this technical problem by enhancing the operation of a circuit-testing software application or a hardware circuit-testing device.

[0037]The number of necessary tests needed to verify a q-module increases as a geometric func...

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Abstract

A method and associated systems for using wreath products and invariance groups to test a partially symmetric quantum-logic circuits. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to hierarchically organize the circuit's inputs into non-overlapping blocks. The system creates set of groups associated with the blocks, and then generates an invariance group that contains one or more invariant permutations of the inputs by computing a wreath product of the set of groups. These invariant permutations identify a minimal number of tests required to verify the circuit for all possible input vectors. The system then directs a test apparatus to perform the resulting optimized test sequence upon the circuit.

Description

[0001]This application is a continuation application claiming priority to Ser. No. 15 / 194,718, filed Jun. 28, 2016.TECHNICAL FIELD[0002]The present invention relates to testing quantum-logic circuits (also known as “q-modules”) and in particular to using group theory and wreath-product computations in order to optimize testing of partially symmetric q-modules.BACKGROUND[0003]Unlike conventional binary logic, quantum logic is not limited to binary states of 0 and 1. Because inputs and outputs of a quantum-logic circuit may assume far more states than those of an analogous binary-logic circuit, a far greater number of tests may be required to fully verify correct operation of the quantum-logic circuit. Testing a q-module comprising larger numbers of inputs and states can therefore be prohibitively expensive or resource-intensive.BRIEF SUMMARY[0004]A first embodiment of the present invention provides a quantum-logic test-development system comprising a processor, a memory coupled to th...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06N99/00H03K19/195
CPCH03K19/195G06N99/002G06N10/00
Inventor JASIONOWSKI, PAWEL
Owner KYNDRYL INC
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