Non-volatile memory array with memory gate line and source line scrambling

a non-volatile memory array and source line technology, applied in semiconductor devices, digital storage, instruments, etc., can solve the problems of higher chance and degree of program disturbance, large memory array size, and higher chip cos

Active Publication Date: 2018-06-14
INFINEON TECH LLC
View PDF1 Cites 1 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent text discusses a method for reducing program disturb in NVM arrays. The method involves using a dedicated source line (SL) architecture or dedicated MG drivers for each NVM cell. This reduces program disturb to unselected cells, but it also requires a large number of additional drivers and connections, leading to higher chip cost. The text also discusses methods for scrambling MGs or SLs to further minimize program disturb. The technical effects of the patent text include reducing program disturb to unselected cells and minimizing program disturb stemming from TPD and PDB on the unselected cells.

Problems solved by technology

However, DSL architecture or dedicated MG drivers may require a large number of additional drivers and connections, causing bigger memory array size and higher chip cost.
As previously discussed, HV biasing in unselected MGs may contribute to higher chance and degree of program disturb caused by TPD and PDB.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Non-volatile memory array with memory gate line and source line scrambling
  • Non-volatile memory array with memory gate line and source line scrambling
  • Non-volatile memory array with memory gate line and source line scrambling

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0020]The following description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a good understanding of several embodiments of the subject matter. It will be apparent to one skilled in the art, however, that at least some embodiments may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in a simple block diagram format in order to avoid unnecessarily obscuring the techniques described herein. Thus, the specific details set forth hereinafter are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the spirit and scope of the subject matter.

[0021]Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions utilizing terms such as “processing”, “computing”, “calc...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A memory device includes a memory array arranged in rows and columns. The memory array may have at least four non-volatile memory (NVM) cells coupled in the same column of the memory array, in which each NVM cell may include a memory gate. The first and second NVM cells of the at least four NVM cells may share a first source region, and the third and fourth NVM cells may share a second source region. The memory gates of the first and second NVM cells may not be electrically coupled with one another, and the first and second source regions may not be electrically coupled with one another. Each of the first and second source regions may be electrically coupled with at least another source region of the same column in the memory array.

Description

PRIORITY[0001]The present application claims the priority and benefit under 35 U.S.C. § 119(e) of U.S. Provisional Application No. 62 / 431,582, filed on Dec. 8, 2016, which is incorporated by reference herein in its entirety.TECHNICAL FIELD[0002]The present disclosure relates generally to a non-volatile memory (NVM) device, and more particularly, to methods and embodiments of grouping and connecting source lines and memory gate lines to reduce effects of program disturb.BACKGROUND[0003]Memory that retains its data even when operation power is not available is classified as non-volatile memory. Examples of non-volatile memory are nvSRAM, ferroelectric RAM (F-RAM), programmable-read-only memory (PROM), erasable-programmable-read-only memory (EPROM), electrically-erasable-programmable-read-only-memory (EEPROM), and flash memories. Some memory arrays utilize transistors and gate structures which may include a charge trapping layer. The charge trapping layer may be programmed to store dat...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & AuthorityApplications(United States)
IPC IPC(8): G11C16/34G11C11/56H10B41/30H10B41/40H10B43/30H10B43/40H10B69/00
CPCG11C16/3427G11C11/5628G11C11/5642H01L29/42344G11C16/0466G11C16/0425G11C16/10G11C16/0483H10B43/30H10B69/00
InventorCHEN, CHUNBETSER, YORAMCHANG, KUO-TUNGGIVANT, AMICHAISHETTY, SHIVANANDAFANG, SHENQING
OwnerINFINEON TECH LLC