Memory apparatus and voltage control method thereof

Abstract

A memory apparatus and a voltage control method of the memory apparatus are provided. The memory apparatus of the invention includes a synchronous circuit, a clock tree and a memory controller. The synchronous circuit receives a reference clock and generating a clock signal. The clock tree is coupled to an output end of the multiplexer and assigns the clock signal to a plurality of signal paths. The memory controller is coupled to the synchronous circuit and controls the synchronous circuit to adjust a frequency of the clock signal according to an operating mode of the memory apparatus.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention[0001]The invention relates to an electronic device, and particularly relates to a memory apparatus and a voltage control method of the memory apparatus.2. Description of Related Art[0002]In order to save energy, integrated circuit designs using different power modes have been widely adopted. In general, in the normal operating power mode, the operation of a circuit inside the integrated circuit can operate at the maximum operating voltage, while in the power saving power mode, the operating voltage is lowered, so as to achieve the purpose of saving energy. In the field of memory, the clock tree is generally used to transfer the system clock to each component in the integrated circuit. When the memory apparatus switches from the power saving mode to a normal mode to access data, it may take too much time for the lowered power supply voltage of the clock tree in the power saving mode to raise to a voltage locked by a delay locked lo...

AI Technical Summary

Benefits of technology

The invention is about a memory device and a way to control voltage to save energy without causing data access errors. The device adjusts the frequency of the clock signal based on its power-saving mode to reduce power consumption and stabilize the voltage supply to the clock tree. This prevents data access errors when switching from the power-saving mode to the normal mode. The technical effect is that the device saves energy without sacrificing data access accuracy.

Problems solved by technology

When the memory apparatus switches from the power saving mode to a normal mode to access data, it may take too much time for the lowered power supply voltage of the clock tree in the power saving mode to raise to a voltage locked by a delay locked loop circuit.

Since the power supply voltage has a great influence on the performance of the clock tree, the significant voltage drop of the power supply voltage of the clock tree in the power saving mode may cause the system clock fails to raise to an expected voltage in a predetermined time when memory apparatus switches to a normal mode to access data, and which may lead to data access errors.

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