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System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction

a cache line and memory ownership technology, applied in the field of memory ownership, can solve problems such as improper or unintended operation, dcache which is a slow and tedious process, and subsequent modification by sm

Active Publication Date: 2017-10-24
VIA ALLIANCE SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a processor that can detect self-modifying code by analyzing cache lines. The processor includes an ownership queue, a fetch system, a processing front end, an executing system, a new destination address comparator, and an executing stale detector. The processor can determine if a cache line is owned by an instruction and can mark the instruction for execution. The executing system can then flush the processor and retrieve an instruction pointer to fetch an instruction from an instruction cache. The technical effect of this invention is to improve the detection and prevention of self-modifying code.

Problems solved by technology

At least one problem with prefetch and OOO operation is that instructions that have been prefetched and forwarded for execution may be subsequently modified by SMC.
Thus, an instruction that is already sent for execution may have missed the modification potentially causing improper or unintended operation.
If the icache attempts to read from memory owned by the dcache, ownership must be transferred from the dcache which is a slow and tedious process which tends to serialize operation.
Although 4 KB is not a significant amount of memory, SMC may cause thrashing of ownership between the icache and the dcache substantially reducing operating efficiency.
It has been observed that even 1 KB ownership granularity was still problematic for SMC in many situations.
Furthermore, larger page sizes are often used, such as 2 megabytes (MB) or even 1 gigabyte (GB), so that ownership granularity has remained a significant issue that reduces overall performance.

Method used

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  • System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction
  • System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction
  • System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction

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Embodiment Construction

[0025]The inventors have recognized the problems of memory ownership in view of self-modifying code (SMC). They have therefore developed a system and method of establishing memory ownership on a cache line basis using an ownership queue which may be used for detecting SMC including modification of cache lines with executing instructions. An ownership index is determined for each cache line entered into the ownership queue. Each cache line is translated into instructions, and a corresponding ownership index is included with each instruction. As each instruction is issued for execution, an executing bit of the corresponding entry in the ownership queue is set. A destination address is determined for each store instruction that has been issued. A new destination address comparator compares each newly determined destination address, when determined, with each cache line address of valid entries stored in the ownership queue to determine any matching entries. An executing stale detector ...

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Abstract

A processor that determines memory ownership on a cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction. An ownership index and corresponding cache line address are entered for each cache line into an ownership queue. The ownership index is provided with each instruction derived from the cache line. When the instruction is issued, an executing bit is set in the corresponding entry. When a destination address of a store instruction matches an entry in the ownership queue, the store instruction is marked to invoke an executing exception if the executing bit of the entry is set. When a store instruction that is ready to retire is marked to invoke the executing exception, the store instruction is allowed to retire, the processor is flushed, and the next instruction after the store instruction is re-fetched to continue processing.

Description

CROSS REFERENCE TO RELATED APPLICATION(S)[0001]This application claims priority based on U.S. Provisional Application, Ser. No. 62 / 324,945, filed Apr. 20, 2016, which is hereby incorporated by reference in its entirety.[0002]This application is related to the following U.S. Patent Applications, each of which has a common assignee and common inventors.[0003]FILINGSer. No.DATETITLE15 / 156,391May 17, SYSTEM AND METHOD OF2016DETERMINING MEMORY OWNERSHIPON CACHE LINE BASIS FOR DETECTINGSELF-MODIFYING CODE INCLUDINGCODE WITH LOOPING INSTRUCTIONS15 / 156,403May 17, SYSTEM AND METHOD OF2016DETERMINING MEMORY OWNERSHIPON CACHE LINE BASIS FOR DETECTINGSELF-MODIFYING CODE INCLUDINGCODE WITH INSTRUCTION THATOVERLAPS CACHE LINE BOUNDARIES15 / 156,416May 17, SYSTEM AND METHOD OF2016DETERMINING MEMORY OWNERSHIPON CACHE LINE BASIS FOR DETECTINGSELF-MODIFYING CODEBACKGROUND OF THE INVENTION[0004]Field of the Invention[0005]The present invention relates in general to memory ownership, and more particularl...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): G06F12/00G06F12/0875G06F12/0891
CPCG06F12/0875G06F12/0891G06F2212/1008G06F2212/452G06F12/0893G06F12/109G06F2212/604G06F2212/657
Inventor BEAN, BRENTEDDY, COLIN
Owner VIA ALLIANCE SEMICON CO LTD
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