System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction

Abstract

A processor that determines memory ownership on a cache line basis for detecting self-modifying code including modification of a cache line with an executing instruction. An ownership index and corresponding cache line address are entered for each cache line into an ownership queue. The ownership index is provided with each instruction derived from the cache line. When the instruction is issued, an executing bit is set in the corresponding entry. When a destination address of a store instruction matches an entry in the ownership queue, the store instruction is marked to invoke an executing exception if the executing bit of the entry is set. When a store instruction that is ready to retire is marked to invoke the executing exception, the store instruction is allowed to retire, the processor is flushed, and the next instruction after the store instruction is re-fetched to continue processing.

Description

CROSS REFERENCE TO RELATED APPLICATION(S)[0001]This application claims priority based on U.S. Provisional Application, Ser. No. 62 / 324,945, filed Apr. 20, 2016, which is hereby incorporated by reference in its entirety.[0002]This application is related to the following U.S. Patent Applications, each of which has a common assignee and common inventors.[0003]FILINGSer. No.DATETITLE15 / 156,391May 17, SYSTEM AND METHOD OF2016DETERMINING MEMORY OWNERSHIPON CACHE LINE BASIS FOR DETECTINGSELF-MODIFYING CODE INCLUDINGCODE WITH LOOPING INSTRUCTIONS15 / 156,403May 17, SYSTEM AND METHOD OF2016DETERMINING MEMORY OWNERSHIPON CACHE LINE BASIS FOR DETECTINGSELF-MODIFYING CODE INCLUDINGCODE WITH INSTRUCTION THATOVERLAPS CACHE LINE BOUNDARIES15 / 156,416May 17, SYSTEM AND METHOD OF2016DETERMINING MEMORY OWNERSHIPON CACHE LINE BASIS FOR DETECTINGSELF-MODIFYING CODEBACKGROUND OF THE INVENTION[0004]Field of the Invention[0005]The present invention relates in general to memory ownership, and more particularl...

AI Technical Summary

Problems solved by technology

At least one problem with prefetch and OOO operation is that instructions that have been prefetched and forwarded for execution may be subsequently modified by SMC.

Thus, an instruction that is already sent for execution may have missed the modification potentially causing improper or unintended operation.

If the icache attempts to read from memory owned by the dcache, ownership must be transferred from the dcache which is a slow and tedious process which tends to serialize operation.

Although 4 KB is not a significant amount of memory, SMC may cause thrashing of ownership between the icache and the dcache substantially reducing operating efficiency.

It has been observed that even 1 KB ownership granularity was still problematic for SMC in many situations.

Furthermore, larger page sizes are often used, such as 2 megabytes (MB) or even 1 gigabyte (GB), so that ownership granularity has remained a significant issue that reduces overall performance.

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