A fast divider with divisor 15í‡2n
A magic instrument and fast technology, applied in the field of fast divider, can solve the problems of many components, complex structure, slow operation speed, etc., and achieve the effect of few components, low cost and simple structure
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Embodiment 1
[0021] The dividend is 0~127×2 n +2 n -1, the divisor is 15×2 n , A divider for fast calculation when n=0. Its circuit schematic diagram is shown as in Fig. 1. Among them, the adder ADD435&ADD515 adopts the circuit schematic diagram shown in Figure 3. The connection relationship of the circuit is that I1, I2, I3, I4, I5, I6, and I7 are the input terminals of the divider, forming the binary dividend I1I2I3I4I5I6I7; I1, I2, I3, I4, I5, I6, I7 are connected to the adders ADD435&ADD515 in turn Pin Y3, Pin Y2, Pin Y1, Pin X4, Pin X3, Pin X2, Pin X1; I1 is connected to pin 1 of XR21 and X3 of adder ADD314 at the same time; I2 is connected to pin 1 of XR22 and XR22 at the same time X2 pin of the adder ADD314; I3 is connected to the XR23 pin 1 of the XOR gate and the X1 pin of the adder ADD314; I4 is connected to the input pin 1 of A2 at the same time; I5 is connected to the XR21 pin 2 of the XR gate at the same time; I6 is connected to the XOR gate at the same time Pin 2 of OR gate XR22;...
Embodiment 2
[0031] The dividend is 0~127×2 n +2 n -1, the divisor is 15×2 n , A divider for fast calculation when n=0. Its circuit schematic diagram is shown as in Fig. 1. Among them the adder ADD435&ADD515 adopts the circuit principle diagram shown in Fig. 4. The connection relationship of the circuit is that I1, I2, I3, I4, I5, I6, and I7 are the input terminals of the divider, forming the binary dividend I1I2I3I4I5I6I7; I1, I2, I3, I4, I5, I6, I7 are connected to the adders ADD435&ADD515 in turn Pin Y3, Pin Y2, Pin Y1, Pin X4, Pin X3, Pin X2, Pin X1; I1 is connected to pin 1 of XR21 and X3 of the adder ADD314 at the same time; I2 is connected to pin 1 of XR22 and XR22 at the same time X2 pin of the adder ADD314; I3 is connected to pin 1 of the exclusive OR gate XR23 and pin X1 of the adder ADD314; I4 is connected to the input pin 1 of A2 at the same time; I5 is connected to pin 2 of the exclusive OR gate XR21; Pin 2 of OR gate XR22; I7 is connected to pin 2 of XR23 at the same time; output...
Embodiment 3
[0041] The dividend is 0~127×2 n +2 n -1, the divisor is 15×2 n , When n=1, the circuit principle diagram of the fast operation divider is shown in Fig. 2. The connection relationship of the circuit is based on Fig. 1 with a line I8 from input to output. 1 -O8 1 . Other circuit connection relations are the same as in the first embodiment.
[0042] When I1I2I3I4I5I6I7I8 1 =(11000111)B=(199)D, because X4, X3, X2, X1 of ADD435&ADD515 constitute the first addend of ADD435&ADD515, Y3, Y2, and Y1 of ADD435&ADD515 constitute the first addition of ADD435&ADD515. Two addends, so the first addend of ADD435&ADD515 in the first addition is (0011)B, and the second addend in the first addition is (110)B, (0011)B+(110)B=(01001 )B, so the result of the first addition of ADD435&ADD515 is 0, 1, 0, 0, 1; the result of the first addition constitutes the first addend of the second addition, and the highest bit of the result of the first addition Form the second addend of the second step of addition, s...
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