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A fast divider with divisor 15í‡2n

A magic instrument and fast technology, applied in the field of fast divider, can solve the problems of many components, complex structure, slow operation speed, etc., and achieve the effect of few components, low cost and simple structure

Inactive Publication Date: 2004-11-17
HEBEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention solves the problems of complex structure, many components and slow operation speed in the existing divider technology, thereby providing a divisor with a divisor of 15×2 n , a fast divider when n is 0 or any positive integer

Method used

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  • A fast divider with divisor 15í‡2n
  • A fast divider with divisor 15í‡2n
  • A fast divider with divisor 15í‡2n

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0024] The dividend is 0~127×2 n +2 n -1, the divisor is 15×2 n , a divider with fast operation when n=0. The schematic diagram of its circuit is shown in Figure 1. The connection relationship of the circuit is that I1, I2, I3, I4, I5, I6, and I7 are the input terminals of the divider, which constitute the binary dividend I1I2I3I4I5I6I7; I1, I2, I3, I4, I5, I6, and I7 are sequentially connected to the adder ADD435 Y3 pin, Y2 pin, Y1 pin, X4 pin, X3 pin, X2 pin, X1 pin; I1, I2, I3 are simultaneously connected to the X3 pin, X2 pin, X1 pin of the adder ADD314; the output F1 pin, F2 pin of the ADD435 , F3, and F4 are connected to the X1, X2, X3, and X4 pins of the adder ADD414 in turn, and are also connected to the input pins 1, 2, 3, and 4 of the AND gate A2 in turn; the output of the ADD435 is F5. Connect the 1 pin of OR gate R1, and connect the Y1 pin of the adder ADD414 at the same time; the output pins F1, F2, F3, and F4 of ADD414 are sequentially connected to the input ...

Embodiment 2

[0033] The dividend is 0~127×2 n +2 n -1, the divisor is 15×2 n , the circuit schematic diagram of the divider of fast operation when n=0 is as shown in Figure 2, and the connection relation of its circuit is that I1, I2, I3, I4, I5, I6, I7 are the input end of divider, constitute the binary system The dividend I1I2I3I4I5I6I7; the output pin 5 of the AND gate A2 is connected to the input pin 2 of the OR gate R1, and is connected to the input pin 1 of the NOT gate N1 at the same time; the output pin 5 of the NOT gate N1 is connected to the input pin 2 of the AND gate A3, A4, A5, and A6 in turn Pin, the output terminals F4, F3, F2, F1 of the adder ADD314 are connected to the output O0 pin O1 pin, O2 pin, O3 pin of the divider in turn, and the output 3 pins of the AND gate A3, A4, A5, A6 are connected to the divider in turn The output terminals O4, O5, O6, O7 constitute the binary remainder O4O5O6O7 of the division result; other circuit connections are the same as those in Embo...

Embodiment 3

[0042] The dividend is 0~255, and the divisor is 15×2 n , the circuit schematic diagram of the divider of fast operation when n=1 is as shown in Figure 3, and the connection relation of its circuit is to increase a connection line I8 from input to output on the basis of Figure 1 1 -O8 1 . When ADD435 adopts four-bit binary numbers plus four-bit binary numbers and five-bit adders, all positions other than the lowest three bits of the second addend are 0. Other circuit connections are the same as in Embodiment 1.

[0043] When I1I2I3I4I5I6I7I8 1 During =(11000111) B=(199) D, because X4, X3, X2, X1 of ADD435 constitute the first addend of ADD435, Y3, Y2, Y1 of ADD435 constitute the second addend of ADD435, the ADD435 like this The first addend is (0011)B, the second addend is (110)B, (0011)B+(110)B=(01001)B, so F5, F4, F3, F2, F1 of ADD435 are respectively 0, 1, 0, 0, 1; ADD435 we use a four-digit binary number plus a four-digit binary number and a five-bit adder to implemen...

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Abstract

The invention is a kind of divider whose divisor is 15í‡2n. The character lies in: it uses different adder, and-gate or not gate to form the divider, the input end is the binary dividend, one output end forms the binary quotient of the dividing result, and another end output the binary remainder of the dividing. The divider can carry on division whose divisor is 15í‡2n, the dividend is 0-1272n +2n -1, (n=0, 1, 2, 3®®n). The divider is simple, the cost is low.

Description

technical field [0001] The invention belongs to a divider in an electronic device, in particular to a divisor whose divisor is 15×2 n , A fast divider when n is 0, 1, 2, 3, ... n integers. Background technique [0002] Among the various operations of digital signal processing, division is the most complex operation with the most potential to be tapped. In general-purpose CPUs and DSPs, a divider is often not specifically implemented with hardware, because the proportion of division in general applications is very small, and the design of the divider is much more complicated than other computing components, so the usual practice It is to write software on the basis of other computing components such as ALU and / or multiplier to form a division subroutine. However, in specific application fields such as number system conversion and data unpacking, the situation is different. If the division operation occupies a considerable proportion, simply using software for division opera...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/52
Inventor 武金木武优西姚芳李艳谢莉莉
Owner HEBEI UNIV OF TECH