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A fast divider with divisor 15í‡2n

A device and fast technology, applied in the field of fast dividers, can solve the problems of slow operation speed, many components and complex structure, and achieve the effect of less components, low cost and simple structure

Inactive Publication Date: 2007-12-05
HEBEI UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The present invention solves the problems of complex structure, many components and slow operation speed in the existing divider technology, thereby providing a divisor with a divisor of 15×2 n , a fast divider when n is an integer of 0, 1, 2, 3, ...

Method used

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  • A fast divider with divisor 15í‡2n
  • A fast divider with divisor 15í‡2n
  • A fast divider with divisor 15í‡2n

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0032] The dividend is 0~119×2 n +2 n -1, the divisor is 15×2 n , a divider with fast operation when n=0. Its circuit connection relationship is shown in Figure 1. I1, I2, I3, I4, I5, I6, and I7 are the input terminals of the divider, which constitute the binary dividend I1I2I3I4I5I6I7; I1, I2, I3, I4, I5, I6, and I7 are connected to the Y3 pin and Y2 pin of the adder ADD435 in turn , Y1 pin, X4 pin, X3 pin, X2 pin, X1 pin; I1, I2, I3 are simultaneously connected to the X3 pin, X2 pin, X1 pin of the adder ADD313; the output F1 pin, F2 pin, F3 pin, F4 of the ADD435 The pins are sequentially connected to the X1 pin, X2 pin, X3 pin, and X4 pin of the adder ADD414, and at the same time with the input pin 1, input pin 2, input pin 3, and input pin 4 of the AND gate A2; the output pin F5 of the ADD435 is connected to the adder ADD414 The input Y1 pin of the OR gate is connected to the input pin 1 of the OR gate R1 at the same time; the output pin 5 of the AND gate A2 is connecte...

Embodiment 2

[0042] The dividend is 0~127×2 n +2 n -1, the divisor is 15×2 n , a divider with fast operation when n=0. Its circuit connection relationship is shown in Figure 2. I1, I2, I3, I4, I5, I6, and I7 are the input terminals of the divider, which constitute the binary dividend I1I2I3I4I5I6I7; I1, I2, and I3 are connected to the input pins 3, 2, and 1 of the AND gate A1; I4 is connected to the AND gate The input pin 4 of A1; the output pin F1, F2 pin, and F3 pin of ADD313 are connected to the output O3 pin, O2 pin, and O1 pin of the divider in turn, and the output pin 5 of the AND gate A1 is connected to the output pin O0 of the divider to form the division result The binary quotient O0O1O2O3; the output pins 3 of the AND gates A3, A4, A5, and A6 are respectively connected to the output terminals O4, O5, O6, and O7 of the divider in turn to form the binary remainder O4O5O6O7 of the division result. Other circuit connections are the same as in Embodiment 1.

[0043] When I1I2I3I4...

Embodiment 3

[0054] The dividend is 0~119×2 n +2 n -1, the divisor is 15×2 n , a divider with fast operation when n=0. Its circuit connection relationship is shown in Figure 3. I1, I2, I3, I4, I5, I6, and I7 are the input terminals of the divider, which constitute the binary dividend I1I2I3I4I5I6I7; the output pin 5 of the AND gate A2 is connected to the input pin 2 of the OR gate R1, and is connected to the input pin 1 of the NOT gate N1 pin; the output pin 5 of the NOT gate N1 is simultaneously connected to the input pin 1 of the AND gate A6, A5, A4, and A3; the output pins F1, F2, and F3 of the ADD313 are sequentially connected to the output pins O3, O2, and O1 of the divider O1O2O3 is the binary quotient of the division result; the output 3 pins of the AND gates A3, A4, A5, and A6 are respectively connected to the output terminals O4, O5, O6, and O7 of the divider in turn to form the binary remainder O4O5O6O7 of the division result. Other circuit connections are the same as in Embo...

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Abstract

The invention is a kind of divider whose divisor is 15x2n. The character lies in: it uses different adder, and-gate or not gate to form the divider, the input end is the binary dividend, one output end forms the binary quotient of the dividing result, and another end output the binary remainder of the dividing. The divider can carry on division whose divisor is 15x2n, the dividend is 0-1272n +2n -1, (n=0, 1, 2, 3-n). The divider is simple, the cost is low.

Description

technical field [0001] The invention belongs to a divider in an electronic device, in particular to a divisor whose divisor is 15×2 n A fast divider for , where n is an integer of 0, 1, 2, 3, .... Background technique [0002] Among the various operations of digital signal processing, division is the most complex operation with the most potential to be tapped. In general-purpose CPUs and DSPs, a divider is often not specifically implemented with hardware, because the proportion of division in general applications is very small, and the design of the divider is much more complicated than other computing components, so the usual practice It is to write software on the basis of other computing components such as ALU and / or multiplier to form a division subroutine. However, in specific application fields such as number system conversion and data unpacking, the situation is different. If the division operation occupies a considerable proportion, simply using software for divisi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/52
Inventor 姚芳武金木武优西李艳周红
Owner HEBEI UNIV OF TECH