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Multi IO extended interface server master board device

A technology for expanding interfaces and servers, which is applied in the field of server motherboard devices with multiple IO expansion interfaces to achieve the effects of strong general-purpose, flexible configuration, and reduced limitations.

Active Publication Date: 2008-02-13
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The technical problem to be solved by the present invention is to provide a server motherboard device with multiple IO expansion interfaces, which overcomes the processing bottleneck of a large number of IO requests in the server in the prior art, and improves the performance of the server motherboard in processing IO requests

Method used

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  • Multi IO extended interface server master board device
  • Multi IO extended interface server master board device
  • Multi IO extended interface server master board device

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Embodiment Construction

[0021] With reference to Fig. 1, make the server motherboard device of many IO expansion interfaces, this embodiment comprises AMD Opteron (Opteron) central processing unit, HT bus controller (comprising 3 AMD8131HT bus bridge bridge chips and 1 AMD8111HT bus I / O hub ), and peripheral expansion slots (including 12 PCI-X slots, 2 PCI slots, 8 DDR memory slots, and a series of low-speed peripheral interface devices), the layout of the PCB (Printed CircuitBoard) board as shown in picture 2.

[0022] The AMD Opteron central processing unit is a 64-bit processor compatible with the standard X86 structure, and its internal structure is shown in Figure 3. In addition to the 64-bit CPU core, the AMD Opteron processor also embeds the north bridge controller in the processor, so that the processor integrates a dual-channel DDR memory interface and 3 HT bus interfaces. AMDOpteron's method of separating the memory interface and the IO interface gets rid of the bandwidth limitation of the...

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Abstract

The present invention includes AMD Opteron central processing unit, HT bus controller, periphery expansion slot, wherein HT bus controller including three AMD 8131 HT bus bridging chip and one AMD 8111 HT bus I / O hub; periphery expansion slot including twelve PCI-X sockets, two PCI sockets, eight DDR memory sockets, and a series of slow speed peripheral interface equipment. The present invention supported all I / O interface adopts universal PCI-X and PCI socket with strong versatility; said invention can support most twelve 64 bit 133MHz PCI-X socket, capable of satisfying different kinds of IO request need with fine expansibility, and according to obligate 8-bite HT bus interface to cascade other HT bus equipment and further enhancing mainboard extended capability. Said invention overcomes a lot of IO request server process bottleneck in current technology, raising server mainboard performance in processing IO request.

Description

technical field [0001] The patent of the present invention relates to the field of computer technology, in particular to a server motherboard device with multiple IO (input output) expansion interfaces, which is suitable for a large number of IO service requests. Background technique [0002] With the continuous advancement of CPU technology, the computing power of various servers is getting stronger and stronger, but the IO processing capacity of the server has not been greatly improved. At present, the commonly used servers can have 1 to 4 32-bit or 64-bit processors, but usually only have 5 PCI expansion slots at most, of which there is usually only one 133MHz PCI-X expansion slot, this expansion capability limits the application of the server . [0003] Another example is a server motherboard using Intel's P64H2 chipset, which can support up to 2 PCI-X channels, and each channel can be connected to 2 PCI-X slots, but because the bandwidth of the central switching interf...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/16
Inventor 解利伟胡鹏刘涛张佩珩孙凝晖
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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