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Bus arbitration method

A technology of bus arbitration and arbitrator, which is applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problems of low componentization, inaccurate control of the response time, and inability to guarantee the top-level arbiter, etc., to achieve the effect of precise control

Inactive Publication Date: 2009-04-22
SHANGHAI MAGIMA DIGITAL INFORMATION
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, the above scheme still has the following shortcomings: first, the difficulty of chip wiring is high; second, the degree of componentization is not high; third, the control of the response time is not precise enough, as detailed below
If the priority of the request is raised through the lower-level arbiter, it may happen that the request gets the response of the arbiter more smoothly (the priority is not raised) but is blocked in the higher-level arbiter, and there is no guarantee that it will Obtain a response from the top-level arbiter within the specified delay; if the priority of the request is raised through the higher-level arbiter, it may occur that the request has been blocked in the lower-level arbiter for more than the specified maximum delay, and cannot Guaranteed to get a response from the top-level arbitrator within the specified delay, the existing technology obviously cannot accurately control the response time of the request

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Embodiment Construction

[0023] In a computing system, main units can be roughly divided into two types, main units with high requirements on delay and main units with high requirements on bandwidth. The request sent by the main unit with high delay requirements needs the bus to respond in time, otherwise it may cause system errors. Taking the digital TV decoding chip as an example, the central processing unit (CPU) and demultiplexing module (DEMUX) have high delay requirements. The main unit of the main unit; the data throughput of the main unit with high bandwidth requirements is large. Taking the digital TV decoding chip as an example, the video decoding module is the main unit with high bandwidth requirements. For the convenience of explanation, the main unit with high delay requirements is referred to as the first type of main unit, its request is the first type of request, its burst (Burst) is the first type of burst, and its stream burst (Stream Burst) It is the first type of serial burst, and ...

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Abstract

The present invention provides a bus arbitration method. Said bus arbitration method is used in bus tiebreaker. Said bus arbitration method has first priority and second priority, in which the second priority is higher than first priority. Said method includes the following steps: giving a life period to request of first priority; backwards timing said lift period; when the described life period is completed, promoting the priority with the described request to be second priority; in which the described life period can be transferred with said request.

Description

technical field [0001] The invention relates to a bus arbitration method. Background technique [0002] The computer system includes a master unit (MASTER) and a slave unit (SLAVE), and the data exchange between the master unit and the slave unit is completed through the bus (BUS). When a master unit wants to access a slave unit, it first sends a request to the bus, and the bus arbiter arbitrates the received request, selects the request with the highest priority order, and the master unit corresponding to the request with the highest priority order can The control bus accesses the corresponding slave units. Each main unit has certain requirements on bus bandwidth (Bandwidth) and delay (Latency). For example, the central processing unit (CPU) has higher requirements on delay, while the video processing module has higher requirements on bandwidth. Generally speaking, the request sent by the master unit with high delay requirement will be given high priority, while the maste...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/362
Inventor 张亚林邓良策
Owner SHANGHAI MAGIMA DIGITAL INFORMATION