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System and method to reduce execution of instructions involving unreliable data in a speculative processor

A speculative execution, processor technology, applied in the system field, can solve the problems of negative impact, conversion table buffer cache pollution, useless results, etc.

Inactive Publication Date: 2009-09-16
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, execution of instructions that consume values ​​resulting from cache misses may negatively impact the benefits achieved through speculative execution
Loads that rely on invalid data do not provide any prefetch benefits and may cause translation look-aside buffer and / or cache pollution
Furthermore, branches that depend on invalid data are often incorrectly decided, causing ad-hoc mode execution to deviate from the branch path indicated by the branch predictor, and / or rendering the result useless

Method used

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  • System and method to reduce execution of instructions involving unreliable data in a speculative processor
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  • System and method to reduce execution of instructions involving unreliable data in a speculative processor

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Embodiment Construction

[0017] A system and method are provided for distinguishing between unusable, unreliable values ​​and usable, reliable values ​​produced during speculative execution of a computer processor. Such speculative execution includes, for example: pipelining, look-ahead, out-of-order processing, and ad-hoc mode execution. In one embodiment, a processor is enabled to selectively cancel instructions and branches involving dependent data resulting from a cache miss. The result is reduced processor power consumption, conserved processor execution resources, and increased processor throughput. In one embodiment, a tag in the form of a single bit is added to each data storage area of ​​the processor, including registers, predicates, flags, etc., to provide a cost-effective way to improve performance and reduce power consumption.

[0018] In some processors, out-of-order (OOO) execution is achieved by buffering speculative instructions in a reorder buffer (ROB) until the instructions becom...

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Abstract

System and method to reduce execution of instructions involving unreliable data in a speculative processor. A method comprises identifying scratch values generated during speculative execution of a processor, and setting at least one tag associated with at least one data area of the processor to indicate that the data area holds a scratch value. Such data areas include registers, predicates, flags, and the like. Instructions may also be similarly tagged. The method may be executed by an execution engine in a computer processor.

Description

technical field [0001] The present invention relates generally to computer processor architecture, and more particularly, to a system and method for marking registers during speculative execution to distinguish usable data from unusable data. Background technique [0002] In the past, computer processors executed instructions one at a time in the order in which they appeared in the processor. As processors have evolved, concepts such as pipelining, looking ahead, out of order processing, and speculative execution have been introduced into most general-purpose computer processors, including those used in personal computers. device. These techniques allow a computer processor to execute individual instructions while waiting for other high-latency instructions to produce their results. The ability to continue executing instructions while waiting for high-latency instructions and to use execution resources is important to achieving high performance in current processors. Whil...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/30
CPCG06F9/3865G06F9/30072G06F9/30101G06F9/383G06F9/3842G06F9/3844
Inventor 克里斯托弗·威尔克森
Owner INTEL CORP