Asynchronous reset circuit and realization method thereof

Abstract

The invention discloses an asynchronous reset circuit and its realization method. The circuit comprises a first register and a second register, and clock input signals are respectively connected to the clock input terminals of the first register and the second register; the external reset signal Connected to the asynchronous reset input terminals of the first register and the second register respectively; the data input terminal of the first register is connected to a logic high level, and its data output terminal is connected to the data input terminal of the second register, and the second register The data output end of the pin is an internal reset signal. The asynchronous reset circuit and its implementation method of the present invention change the uncertain phase relationship between the rising edge of the clock and the transition edge of the reset signal into a definite phase relationship through the latching of the two-stage register and under the action of two clock cycles , to achieve the effect of improving the reliability of asynchronous reset.

Description

technical field [0001] The invention relates to an asynchronous reset circuit and method, in particular to the asynchronous reset circuit and its realization method in various IC products. Background technique [0002] In the existing field of communication electronics, an asynchronous reset circuit is unavoidable for any IC. For example, the reset when the system is powered on is an asynchronous reset. Generally, the asynchronous reset method of the IC chip is directly connected to the asynchronous reset terminal of the internal register through the external reset pin. [0003] Under this existing scheme, the relationship between the cancellation of the reset signal and the corresponding clock phase is uncertain, such as figure 1 As shown, it is a schematic diagram of the timing relationship between the asynchronous reset signal and the clock in the prior art. In the prior art, the external reset pin is directly connected to the asynchronous reset terminal of the internal ...

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Problems solved by technology

[0004] figure 1 The rising edge of the external reset signal is represented by three dotted lines, which shows that the edge of the reset signal cancellation may be before the rising edge of the clock, or after the rising edge of the clock, or even on the edge of the clock; at this time, it is possible It will cause all the registers in the system not to exit the reset state at the same time; some internal registers are still in the reset state, and some registers have entered the working state, resulting in uncertain internal register states and unreliable reset. Therefore, the reset scheme of the prior art is reliable. poor sex

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