Asynchronous reset circuit and realization method thereof

Abstract

The circuit comprises a first register and a second register. The clock signal is respectively connected to the clock inputs of the first register and second register; the external reset signal is respectively connected to the asynchronous reset inputs of the first register and second register; the data input of the first register is connected to the logic high level, and its data output is connected to the data input of the second register; the data output of the second register is an internal reset signal. By the latch of two registers, at the action of two clock cycles, the uncertain phase relation between the clock rising edge and the reset signal jumping edge can become a certain phase relation so as to improve the reset reliability.

Description

technical field [0001] The invention relates to an asynchronous reset circuit and method, in particular to the asynchronous reset circuit and its realization method in various IC products. Background technique [0002] In the existing field of communication electronics, an asynchronous reset circuit is unavoidable for any IC. For example, the reset when the system is powered on is an asynchronous reset. Generally, the asynchronous reset method of the IC chip is directly connected to the asynchronous reset terminal of the internal register through the external reset pin. [0003] Under this existing solution, the relationship between the cancellation of the reset signal and the corresponding clock phase is uncertain, as shown in Figure 1, which is a schematic diagram of the timing relationship between the asynchronous reset signal and the clock in the prior art. The pin is directly connected to the asynchronous reset terminal of the internal register. Due to the uncertain re...

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Problems solved by technology

[0004] The rising edge of the external reset signal in Figure 1 is represented by three dotted lines, which shows that the edge of the reset signal cancellation may be before the rising edge of the clock, or after the rising edge of the clock, or even on the edge of the clock; at this time It may cause all registers in the system not to exit the reset state at the same time; some internal registers are still in the reset state, and some registers have entered the working state, resulting in uncertain internal register states and unreliable resets. Therefore, the reset state of the prior art Poor program reliability

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