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Storage unit, integrated circuit and manufacturing method of the storage unit array

A memory cell and conductivity type technology, which is applied in the manufacture of integrated circuits and memory cell arrays, and in the field of memory cells, can solve the problems of aggravating the problem of non-uniform threshold voltage and increasing the ratio.

Active Publication Date: 2010-02-10
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This means that the ratio of the channel sides to the overall channel width becomes larger, so the non-uniform threshold voltage problem caused by the variation of the trapped charge along the channel sides is gradually exacerbated

Method used

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  • Storage unit, integrated circuit and manufacturing method of the storage unit array
  • Storage unit, integrated circuit and manufacturing method of the storage unit array
  • Storage unit, integrated circuit and manufacturing method of the storage unit array

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Embodiment Construction

[0092] Please refer to the following instructions Figures 1 to 18c To understand the various embodiments of the present invention.

[0093] figure 1 It is a schematic diagram of a part of a NAND gate array, in which the shallow trench isolation is located in area 10, and the side pocket implants are located in areas 11 and 12. The memory cells are located in series of NAND gates, where figure 1The first series of NAND gates includes storage units 16-1 to 16-N connected in series, and the second series of NAND gates includes storage units 26-1 to 26-N connected in series, and N can be 16, 32 or higher values. The corresponding word line WL 1 to WL N The collection of NAND gates is coupled to the corresponding memory cells in the series of NAND gates. The selection of the series of NAND gates is achieved by controlling the block transistors 15, 25 and the source selection transistors 17, 27, wherein the former uses The control line BLT is used to connect the memory cells ...

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Abstract

A charge trapping memory cell is described, having pocket implants along the sides of the channel and having the same conductivity type as the channel, and which implants have a concentration of dopants higher than in the central region of the channel. This effectively disables the channel in the region of non-uniform charge trapping caused by a bird's beak or other anomaly in the charge trappingstructure on the side of the channel. The pocket implant can be formed using a process compatible with standard shallow trench isolation processes.

Description

technical field [0001] The present invention relates to a nonvolatile memory device, in particular to a manufacturing method of a storage unit, an integrated circuit and a storage unit array. Background technique [0002] Flash memory is a memory cell that stores charge between the channel and the gate of a field effect transistor. Since the stored charge affects the threshold voltage of the transistor, the change in the threshold voltage can be used to represent data. [0003] A floating gate memory cell is a widely used charge storage memory cell. In the floating gate memory cell, a gate composed of a conductive material (such as conductive type polysilicon) is formed on a tunneling dielectric, and An interpoly dielectric is formed on the floating gate to separate it from the word line or control gate of the memory cell. Although this technology has been used quite successfully, as the size of the memory cells and the distance between the memory cells are getting smaller ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/792H01L29/06H01L27/115H01L21/8247
Inventor 吕函庭
Owner MACRONIX INT CO LTD