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Method and processorfor prefetching instruction lines

A technology of data lines and processors, applied in the direction of electrical digital data processing, instruments, memory systems, etc., which can solve problems such as cache misses, processor inefficiencies, and incorrect assumptions

Inactive Publication Date: 2007-08-08
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in some cases, this assumption may prove to be incorrect, whereby instructions access data in D-lines that are not located near the current D-line, thus causing cache misses and processor inefficiencies

Method used

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  • Method and processorfor prefetching instruction lines
  • Method and processorfor prefetching instruction lines
  • Method and processorfor prefetching instruction lines

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Embodiment approach

[0049] According to one embodiment, the I line may also store other effective addresses (eg, EA2) and control bits (eg, CTL). As described below, other effective addresses may be used to prefetch the I-line containing instructions targeted by branch instructions in the I-line or additional D-lines. The control bits CTL may include one or more bits indicating the history (DAH) of the data access instruction and the location (LOC) of the data access instruction. The use of this information stored in the I-line is also described below.

[0050]In one embodiment of the invention, the effective address bits and control bits described here can be stored in otherwise unused bits of the I line. For example, each information line in L2 cache 112 may have extra data bits that may be used for error correction (e.g., error correcting code, ECC, with to ensure that the transmitted data is not corrupted and to repair any corruption that occurs). In some cases, each level of cache (eg, L2...

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PUM

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Abstract

Embodiments of the present invention provide a method and apparatus for prefetching instruction lines. In one embodiment, the method includes fetching a first instruction line from a level 2 cache, extracting, from the first instruction line, an address identifying a first data line containing data targeted by a data access instruction contained in the first instruction line or a different instruction line; and prefetching, from the level 2 cache, the first data line using the extracted address.

Description

technical field [0001] The present invention relates generally to the field of computer processors. More specifically, the present invention relates to cache mechanisms used by computer processors. Background technique [0002] Modern computer systems typically contain several integrated circuits (ICs), which include processors, that can be used to process information within the computing system. Data processed by a processor may include computer instructions executed by the processor and data manipulated by the processor using the computer instructions. Computer instructions and data are typically stored in main memory in computer systems. [0003] Processors typically process instructions by executing them in a series of small steps. In some cases, a processor may be pipelined in order to increase the number of instructions being processed by the processor (and thus increase the speed of the processor). Pipelining refers to the provision of separate stages in a process...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08
CPCG06F12/0862
Inventor 戴维·A·卢克
Owner INT BUSINESS MASCH CORP