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Method and system for processing an I/O address translation cache miss

A technology of address conversion and cache, which is applied in the field of I/O address conversion and can solve problems such as sorting problems

Inactive Publication Date: 2007-10-17
INT BUSINESS MASCH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Another problem with this scheme is that when an I / O address translation miss occurs, there may be multiple commands from the I / O device being processed by the CPU
Doing so can create ordering issues with commands that cause I / O address translation cache misses

Method used

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  • Method and system for processing an I/O address translation cache miss
  • Method and system for processing an I/O address translation cache miss
  • Method and system for processing an I/O address translation cache miss

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Embodiment Construction

[0017] Embodiments of the present invention generally provide an improved technique for handling I / O address translation cache misses caused by I / O commands within a CPU. For some embodiments, the CPU hardware may buffer I / O commands that cause I / O address translation cache misses in the command queue until the I / O address translation cache is updated with the necessary information. When the I / O address translation cache has been updated, the CPU can re-issue the I / O command in the command queue, translate the address of the I / O command at the appropriate time, and execute said command as if it were a cache miss Nothing has happened. In this way, the I / O device does not need to handle error responses from the CPU, the I / O commands are processed by the CPU, and the I / O commands are not discarded.

[0018] Hereinafter, embodiments of the present invention will be described. It should be understood, however, that the invention is not limited to specific described embodiments. ...

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PUM

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Abstract

Embodiments of the present invention generally provide an improved technique to handle I / O address translation cache misses caused by I / O commands within a CPU. For some embodiments, CPU hardware may buffer I / O commands that cause an I / O address translation cache miss in a command queue until the I / O address translation cache is updated with the necessary information. When the I / O address translation cache has been updated, the CPU may reissue the I / O command from the command queue, translate the address of the I / O command at a convenient time, and execute the command as if a cache miss did not occur. This way the I / O device does not need to handle an error response from the CPU, the I / O command is handled by the CPU, and the I / O command is not discarded.

Description

technical field [0001] The present invention generally relates to I / O address translation within a central processing unit. Background technique [0002] Computing systems often include a central processing unit (CPU). Typically, other devices within the system issue requests to the CPU to execute commands. Examples of devices that may issue command requests to the CPU include video cards, sound cards, or I / O (input / output) devices within the system. I / O devices can send commands to the CPU for processing. A command from an I / O device can target a memory address and refer to that memory address by an I / O virtual memory address. If the command involves an I / O virtual memory address, the CPU must translate the I / O virtual memory address to a corresponding physical memory address before executing the command. [0003] To provide faster access to data and instructions, and to better utilize the CPU, a CPU may have multiple caches. A cache is a type of memory that is usually...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/10
CPCG06F12/1027G06F12/1081
Inventor 查德·B.·麦克布里德安德鲁·H.·沃特雷恩约翰·D.·艾利史
Owner INT BUSINESS MASCH CORP