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Memory control with selective retention

A selective, memory cell technology, applied in the field of memory circuits, can solve problems such as not being able to adapt

Active Publication Date: 2007-10-24
TELEFON AB LM ERICSSON (PUBL)
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Also, the size relationship between the retention SRAM portion and the non-retention SRAM portion is fixed during operation and may not be able to accommodate

Method used

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  • Memory control with selective retention
  • Memory control with selective retention

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Experimental program
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Embodiment Construction

[0020] Preferred embodiments will now be described in terms of SRAM circuits, such as embedded SRAMs for power critical applications.

[0021] Fig. 1 shows a schematic block diagram of an SRAM structure according to a first preferred embodiment, which can be configured as an integrated memory circuit, and which includes a memory section represented by a dotted box on the right-hand part of Fig. 1, and is divided into SRAM Unit C 0,0 to C y,z groups 30-1 to 30-n. Each group is controlled by a dedicated control circuit comprising input terminals DR1 to DRn of data holding identifiers, logic units L1 to Ln, and gate or switch units S1 to Sn. In addition, the control circuit may also receive a global activity control signal A configured to set the memory circuit to a standby state or mode or to an active state or mode. The number of storage units in each of the groups 30-1 to 30-n can be selected as required, and the number determines the granularity of the retention control. ...

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PUM

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Abstract

The invention relates to a storage circuit and a method that is used for controlling data hold in the storage circuit; wherein, the invention selectively switches a power source signal to a corresponding virtual power source wire from at least two virtual power source wires (24), and each virtual power source wire is shared by a corresponding group from multiple groups of storage units (C0, 0 to Cy, z,). The invention controls the selective switch according to a global activity control signal (A) and a local data hold indicating signal (DR1 to DRn), the global activity control signal (A) is used for setting the storage circuit to standby state or active state, and the local data preservation indicating signal (DR1 to DRn) is assigned to the storage units in a private group, and consequently a data hold part of the storage circuit can fit for applications and application states, and the electric current leaked in a standby mode is consumed only in the storage units that really need to implement data hold.

Description

technical field [0001] The present invention relates to a memory circuit having a plurality of memory cells for storing data, and to a method of controlling data retention in such a memory circuit. Background technique [0002] Random access memory typically includes an array of data storage locations, known as memory cells, where individual data elements, known as bits, can be held. Each memory cell can be addressed such that data from the external environment can be written to the memory cell, or data can be read from the memory cell and provided to the external environment. The time it takes to access data in any particular memory location is essentially independent of location, hence the name Random Access Memory. The word "static" in static random access memory (SRAM) refers to the memory's ability to hold data without having to constantly refresh or rewrite memory cells. This contrasts with "dynamic" random access memory (DRAM), which requires the memory cells to be ...

Claims

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Application Information

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IPC IPC(8): G11C5/14
CPCG11C5/14G11C7/00G11C11/41
Inventor 科内利斯·H·范贝克莱
Owner TELEFON AB LM ERICSSON (PUBL)