Memory control with selective retention
A selective, memory cell technology, applied in the field of memory circuits, can solve problems such as not being able to adapt
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[0020] Preferred embodiments will now be described in terms of SRAM circuits, such as embedded SRAMs for power critical applications.
[0021] Fig. 1 shows a schematic block diagram of an SRAM structure according to a first preferred embodiment, which can be configured as an integrated memory circuit, and which includes a memory section represented by a dotted box on the right-hand part of Fig. 1, and is divided into SRAM Unit C 0,0 to C y,z groups 30-1 to 30-n. Each group is controlled by a dedicated control circuit comprising input terminals DR1 to DRn of data holding identifiers, logic units L1 to Ln, and gate or switch units S1 to Sn. In addition, the control circuit may also receive a global activity control signal A configured to set the memory circuit to a standby state or mode or to an active state or mode. The number of storage units in each of the groups 30-1 to 30-n can be selected as required, and the number determines the granularity of the retention control. ...
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